Thermal characterization of multicolor LED luminaire

The LED based dynamic lighting scheme, require compact and thermally efficient luminaire. This paper presents the thermal investigation on the conceptual design of 36 W multicolor light emitting diode (LED) luminaire. The developed prototype design includes configuration and placement of the multichip LED package, RGBW and single die amber LEDs in a 5 × 3 array on the heat sink. LED configurations with low power input are placed between the LEDs having the high power input. The proposed configuration and placement of LEDs reduces the local heat concentration in the centre region of the heat sink. The temperature of 72 °C at LED chip base plate is reduced to 32.1 °C on the heat sink surface. The numerical results are experimentally validated. The proposed method contributes to a reduction in the size of the luminaire and also enhancement of heat dissipation for improving the longevity of the multicolor based LED luminaire.     

Simulation of LED based luminaires by using multi-domain compact models of LEDs and compact thermal models of their thermal environment

Fast and accurate prediction of hot lumens of LEDs installed in luminaires is an important step in the design of robust and reliable products. A possible approach to this is to create a multi-domain circuit model of a complete LED chip + package + luminaire system that can be simulated by any Spice-like circuit simulator with electro-thermal capabilities. Many LED chip and LED package models and modeling techniques have been published recently, but compact thermal modeling of luminaires as multi heat-source system was not yet dealt with in the literature. This paper aims to fill this gap be describing a systematic approach for system (luminaire) level analysis aimed at solving the combined thermal, electrical and light output simulation problem consistently by describing a method for creating a compact thermal model of LED luminaries with an approach borrowed from the layout based electro-thermal simulation of analog ICs. The applicability of the described method is demonstrated with a real life example, including the validation of the results with thermal measurements.     

Light output stabilisation of LED based streetlighting luminaires by adaptive current control

Temperature dependence of LED operation is often not fully considered during the design of solid state lighting products. If temperature dependence is not carefully considered, solid-state lighting products are typically overdesigned to be too robust enough to fulfil the requirements under any possible environmental conditions. Temperature dependent nature of LEDs though, could even be a new benefit if properly considered. Overdesign means designing for the worst case that is the highest possible environmental temperature when LED efficiency/efficacy is low. With a control scheme resulting in constant emitted total luminous flux significant electrical power saving can be achieved since at lower temperatures, due to increasing efficiency/efficacy less electrical power, thus, lower forward current levels are sufficient. This paper describes different methods to specify the so called iso-flux control of LEDs' operating point, in which effect of temperature changes on light output characteristics is compensated by adjustment of the forward current. Parameters for an automated temperature compensation can be identified with the help of multi-domain LED models. This paper describes our LED multi-domain model based approach applied to the design of the light output control of an existing street-lighting luminaire. During the design of the control scheme real, archived meteorological temperature data set was considered. Based on our model we implemented the temperature compensated iso-flux control of a luminaire and the planned operation was validated by actual measurements. The verified luminaire model was further investigated with multi-domain models of aged LEDs obtained during an LM-80 standard compliant aging of a set of LEDs, characterizing LEDs up to 6000 + h of operating life time.     

Thermal/luminescence characterization and degradation mechanism analysis on phosphor-converted white LED chip scale packages

According to the requirements on minimizing the package size, guaranteeing the performance uniformity and improving the manufacturing efficiency in LEDs, a Chip Scale Packaging (CSP) technology has been developed to produce white LED chips by impressing a thin phosphor film on LED blue chips. In this paper, we prepared two types of phosphor-converted white LED CSPs with high color rendering index (CRI > 80, CCT ~ 3000 K and 5000 K) by using two mixed multicolor phosphor materials. Then, a series of testing and simulations were conducted to characterize both short- and long-term performance of prepared samples. A thermal analysis through both IR thermometry and electrical measurements and thermal simulation were conducted first to evaluate chip-on-board heat dissipation performance. Next, the luminescence mechanism of multicolor phosphor mixtures was studied with the spectral power distribution (SPD) simulation and near-field optical measurement. Finally, the extracted features of SPDs and electrical current-output power (I-P) curves measured before and after a long-term high temperature accelerated aging test were applied to analyze the degradation mechanisms. The results of this study show that: 1) The thermal management for prepared CSP samples provides a safe usage condition for packaging materials at ambient temperature; 2) The Mie theory with Monte-Carlo ray-tracing simulation can be used to simulate the SPD of Pc-white LEDs with mixed multicolor phosphors; 3) The degradation mechanisms of Pc-white LEDs can be determined by analyzing the extracted features of SPDs collected after aging.     

Fluid–solid coupling thermo-mechanical analysis of high power LED package during thermal shock testing

The virtual design by numerical simulation to model various accelerated reliability testing conditions is adopted to validate and improve the reliability of the high power LED package. In this study, the reliability of the high power LED package during thermal shock testing is investigated by fluid–solid coupling thermo-mechanical modeling by considering nonlinear time and temperature dependent material properties. Through fluid–solid coupling transient thermal transfer analysis, it is found that the maximum thermal gradient exceeds 75 K during the rapid cooling process and 91 K during the rapid heating process of the thermal shock testing which is ignored in the traditional isothermal assumption. The calculation results indicate that the equivalent plastic strain range of the bonding wire within the LED package with consideration of the temperature gradient is much higher than that with the isothermal assumption. The assumption of the isothermal condition is not appropriate which will lead to overestimation of the predicted lifetime. The viscoelastic behaviors of the silicone have significant influences on the lifetime prediction of the bonding wire and silicone with low elastic modulus and coefficient of thermal expansion (CTE) can significantly enhance the reliability of the bonding wire under the thermal shock loading. The results in this study could provide a guideline on design for reliability in the high power LED packaging.     

A novel multiple-stress-based predictive model of LEDs for rapid lifetime estimation

This paper proposes a novel multiple-stress-based predictive model (MSBPM) to rapidly assess the lifetime of light-emitting diodes (LEDs). The MSBPM addresses the lifetime estimation of LEDs with respect to temperature, humidity, and current; these three stresses are rarely considered simultaneously in the assessment of reliability. Using several degradation data sets from accelerated life tests (ALTs) without using extrapolation method, a designed adaptive genetic algorithm is employed to identify five unknown parameters of the MSBPM. A simulation of the proposed MSBPM is presented as validation. By applying the degradation data from the ALTs under high stresses, an MSBPM for the LEDs is established. Under the nominal conditions of 25 °C/22.5% RH and a current of 0.35 A, the lifetime of the LED is estimated using the established MSBPM. The effectiveness of the proposed MSBPM is further verified through the estimated results.     

Voltage dependent degradation of HfSiON/SiO2 nMOSFETs under positive bias temperature instability

This paper investigates voltage-dependent degradation of HfSiON/SiO₂ nMOSFETs under conditions of positive bias temperature instability (PBTI), and proposes a PBTI degradation model that can use data from acceleration tests to predict device lifetime accurately. Experimental results show that the PBTI stress generated shallow traps in HfSiON and the exponent of power-law for threshold-voltage shift increased exponentially with an increase of PBTI stress voltage. An enhancement factor that represents creation of shallow charge traps in gate dielectric by PBTI stress was included in the proposed model. The proposed model predicted operational lifetime t_L = 1.64 × 10¹⁰ s, which agreed well with the t_L = 1.92 × 10¹⁰ s measured at low gate stress voltage, whereas the conventional model overestimates t_L by an order of magnitude, demonstrating that the proposed model is very useful on shortening the measurement time for estimating t_L of high-k nMOSFETs.     

Lifetime tests of 600-V GaN-on-Si power switches and HEMTs

We present the first systematic lifetime tests which show excellent long-term reliability for 600 V GaN-on-Si power switches.High voltage accelerated life testing in the OFF-state yields a field related mean-time-to-failure (MTTF) greater than 3 × 10⁸ h for a 600 V operating condition. High temperature accelerated testing in the ON-state gives an MTTF of about 6 × 10⁸h at a 150 °C use condition. High temperature operating life testing using hard switched boost converters at 175 °C shows no measurable device degradation after 3000 h of operation. These results show that the intrinsic reliability of the new device technology is more than adequate for commercial and industrial power electronics applications.     

Reliability and optical properties of LED lens plates under high temperature stress

In this investigation the thermal degradation mechanisms of Bisphenol A Polycarbonate (BPA-PC) plates at the temperature range 100–140 °C are studied. The BPA-PC plates are currently used both in light conversion carriers in LED modules and optical lenses in LED-based products. In this study BPA-PC plates are aged at elevated temperature of 100–140 °C for a period up to 3000 h. Optical and chemical properties of the thermally-aged plates were studied using UV–Vis spectrophotometer, FTIR–ATR spectrometer, and integrated sphere. The results show that increasing the thermal ageing time leads to yellowing, loss of optical properties, and decrease of the light transmission and of the relative radiant power value of BPA-PC plates. The results also depict that there is not much discoloration within the first 1500 h of thermal ageing. The rate of yellowing significantly increases at the end of this induction period. Formation of oxidation products is identified as the main mechanism of yellowing. An exponential-based reliability model is also presented to calculate the rate of degradation reaction and to predict the life-time of BPA-PC plates.     

Modeling of ESR in metallized film capacitors and its implication on pulse handling capability

Metallized film capacitors (MFC) are widely used in pulsed power systems and power electronics applications. The pulse handling capability of MFC is one of important performances and drastically depends on the quality of contact states between the spray and metallization. The equivalent series resistance (ESR) is a significant parameter to the capacitor. This paper presents a model to calculate ESR with consideration of the end contact status. This model shows that ESR at low frequency (∼100 Hz) is more efficient to reflect the end contact status than that at high frequencies (∼10 kHz). Lifetime experiments are designed to demonstrate that MFC with significantly lower ESR enjoy longer pulse lifetime and better pulse handling capability. Thus measured at low frequency (∼100 Hz) can be regarded as a parameter to reflect the disconnections of weak contact in high current densities applications and to evaluate the pulse handling capability.     

Stressing organic light-emitting diode under constant-brightness driving mode

The degradation of the organic light-emitting diodes (OLEDs) was studied under the constant-brightness driving mode. The time-dependent current exhibits a long period of linear increase followed by an exponential increase before the eventually catastrophic failure featured by a vertical increase. A new lifetime T_th is defined as the time for the device to reach the end of the linear increase stage. Similar to the well-known relation between the lifetime and the brightness in the constant-current driving mode, the lifetime and the brightness in the constant-brightness driving mode also fit the formula Lⁿ × T_th = Const., where L is the brightness and n is the acceleration exponent. By examining the current density–voltage–luminance characteristics and the photoluminescence intensity of the devices before and after the stress, it is found that both the reduction of the charge injection efficiency, and the loss of the emissive centers, contribute to the OLEDs’ degradation. The extra power supplied to the device to keep the brightness constant, raises the junction temperature, and eventually leads to the catastrophic failure of the devices.     

The optimum fin width in p-MuGFETs with the consideration of NBTI and hot carrier degradation

Generally it is known that NBTI degradation increases with decrease of a channel width in p-MOSFETs but hot carrier degradation decreases. In this work, a guideline for the optimum fin width in p-MuGFETs is suggested with consideration of NBTI and hot carrier degradation. Using the device lifetime defined as the stress time necessary to reach ΔV_TH = 10 mV, the optimum fin widths have been extracted for different stress voltages and temperatures. When a fin width is narrower than the optimum fin width, the device lifetime is governed by the NBTI degradation. However, when fin width is wider than the optimum fin width, the device lifetime is dominantly governed by hot carrier degradation. The optimum fin width decreases with the increase of the stress voltage but it increases with the increase of the stress temperature.     

End of life and acceleration modelling for power diodes under high temperature reverse bias stress

This work is motivated by the growing importance of lifetime modelling in power electronics. Strongly accelerated High Temperature Reverse Bias (HTRB) testing of power diodes at different stress conditions is performed until alterations and fatigue mechanisms become evident. Two categories of effects can be separated: Drifting breakdown voltage and hard failures with complete loss of blocking capability. Nevertheless the overall stress duration needed to provoke destructive failures is very high with test durations > 2500 h even at almost 230 °C and 100% rated voltage. For both mechanisms the temperature and voltage acceleration is evaluated. Especially temperature acceleration is significant in the regime of testing between 200 °C and 230 °C and an activation energy E_a in the regime > 1 eV can be deduced which is higher compared to values commonly reported in the literature. Failure analysis shows that both package and also chip related effects could contribute to the observed hard failures in HTRB stress under extreme conditions.     

Lifetime and manufacturability of integrated power electronics

In case of battery electric cars, market data show a traditional exponential gradient of sales figures, known from other technology transitions. The worldwide installed wind and photovoltaic capacity show also an exponential gradient. Even the power density of power electronics is growing exponentially.Power electronics is a prerequisite to enable the exponential growth of power density.Requirements on power electronic packaging technologies are electric performance, thermal performance and robust design. Due to the lack of bond wires, SMD capacitors can be mounted close to semiconductors, resulting in a minimization of parasitic inductance. Thermally, the packaging technology benefits from heat spreading inside the copper leadframe and thin dielectric layers. It obtains a thermal resistance of 0.5 K/W, and there is potential to further reduce the thermal resistance by alternative dielectric material. The thermal resistance can be further reduced to at least 0.42 K/W by the construction of a double side chip cooling.A robust design can be offered by the combination of a chip copper metallization connecting to copper microvias connecting to the top copper layer, which means no difference in coefficients of thermal expansion. On the bottom side, a silver sinter layer offers a reliable connection between chip and leadframe.This paper describes production process optimizations, thermal optimization possibilities, power cycling lifetime measurements and first conductive anodic filament lifetime measurements at 1000 V DC. The outlook onto an integrated 120 A 700 V SiC MOSFET demonstrator is given.     

Impacts of NBTI/PBTI on performance of domino logic circuits with high-k metal-gate devices in nanoscale CMOS

Negative-bias temperature instability (NBTI) and positive-bias temperature instability (PBTI) weaken PFETs and high-k metal-gate NFETs, respectively. This paper provides comprehensive analyses on the impacts of NBTI and PBTI on wide fan-in domino gates with high-k metal-gate devices. The delay degradation and power dissipation of domino logic, as well as the Unity Noise Gain (UNG) are analyzed in the presence of NBTI/PBTI degradation. It has been shown that the main concern is the degradation impact on delay which can increase up to 16.2% in a lifetime of 3 years. We have also proposed a degradation tolerant technique to compensate for the NBTI/PBTI-induced delay degradation in domino gates with a negligible impact on UNG and power.     

LER and spacing variability on BEOL TDDB using E-field mapping: Impact of field acceleration

Understanding the impact of process variability on TDDB is crucial for assuring robust reliability for current and future technology nodes. This work introduces a lifetime prediction model that considers local field enhancement to assess the combined impact of die-to-die spacing variability and line edge roughness. The model is applied to 16 nm half-pitch BEOL interconnects assuming either the power law or the root-E as field acceleration model and the impact on lifetime reduction is discussed. In comparison with the ideal case of a straight line with a nominal spacing of 16 nm, a 1-sigma spacing variation of 0.6 nm and 1-sigma LER of 1 nm leads to ~ 3 orders of magnitude lifetime reduction when assuming power-law whereas this value is ~ 1 order of magnitude when assuming root-E.     

Degradation of all-inkjet-printed organic thin-film transistors with TIPS-pentacene under processes applied in textile manufacturing

Printed electronics represent an alternative solution for the manufacturing of low-temperature and large area flexible electronics. The use of inkjet printing is showing major advantages when compared to other established printing technologies such as gravure, screen or offset printing, allowing the reduction of manufacturing costs due to its efficient material usage and the direct-writing approach without requirement of any masks. However, several technological restrictions for printed electronics can hinder its application potential, e.g. the device stability under atmospheric or even more stringent conditions. Here, we study the influence of specific mechanical, chemical, and temperature treatments usually appearing in manufacturing processes for textiles on the electrical performance of all-inkjet-printed organic thin-film transistors (OTFTs). Therefore, OTFTs where manufactured with silver electrodes, a UV curable dielectric, and 6,13-bis(triisopropylsilylethynyl) pentance (TIPS-pentacene) as the active semiconductor layer. All the layers were deposited using inkjet printing. After electrical characterization of the printed OTFTs, a simple encapsulation method was applied followed by the degradation study allowing a comparison of the electrical performance of treated and not treated OTFTs. Industrial calendering, dyeing, washing and stentering were selected as typical textile processes and treatment methods for the printed OTFTs. It is shown that the all-inkjet-printed OTFTs fabricated in this work are functional after their submission to the textiles processes but with degradation in the electrical performance, exhibiting higher degradation in the OTFTs with shorter channel lengths (L = 10 μm).     

A liquid cooling solution for temperature redistribution in 3D IC architectures

The advancement of contemporary three-dimensional integrated circuit (3D IC) technologies offers a promising solution for the insatiable demand of the consumer electronics market. The increased complexity of 3D IC design permits the execution of multiple applications at greater speeds whilst remaining within the design constraints of energy consumption, yield and time-to-market. However, the increased computing performance and compact size may introduce a thermal barrier inhibiting performance, particularly in the case where multiple logic die are stacked and co-aligned hotspots are induced. To mitigate this thermal barrier a novel integrated active thermal solution is investigated in this paper whose purpose is to alleviate hotspots in a contemporary two-die 3D IC architecture. The solution employs a series of integrated microchannels, which permits the transfer of heat, via a coolant, from lower to upper strata. This microfluidic system is driven by a series of integrated AC electrokinetic pumps embedded in the channel walls. Recent advancements in electrokinetic micropump technology have allowed greater increases in fluid velocity – to an order of mm/s – while operating within the voltage constraints of a 3D IC. Numerically qualitative and quantitative temperature distributions are presented for a 3D IC chip design both with and without microchannels for a constant heat flux on the active layer of each silicon chip. The implementation of a microchannel network is shown to alter the thermal distribution map within a 3D IC package creating hot and cold zones with variations on temperature of ?14.6 °C≤ΔT≤9.8 °C with a ΔT_max of ?6.5 °C in the silicon die stack (equivalent to a total maximum heat flux, q_max″, of approximately 112.5 W/cm²). Increasing bulk fluid velocity, within the range 1.3 mm/s≤u_avg≤13 mm/s, can vary the area of the cold zone enhancing heat transfer and reducing the temperature of the die stack without an overall temperature change in the package.     

Ultra-thin alumina layer encapsulation of bulk heterojunction organic photovoltaics for enhanced device lifetime

Successful organic photovoltaic (OPV) device fabrication is contingent on selecting an effective encapsulation barrier layer to preserve device functionality by inhibiting atmosphere-induced degradation. In this work, ultra-thin AlO_x layers are deposited by atomic layer deposition (ALD) to encapsulate pre-fabricated OPV devices. A summary of ALD recipe effects (temperature, cycling time, and number of cycles) on AlO_x film growth and device longevity is presented. First, AlO_x film growth on the hydrophobic OPV surface is shown to occur by a 3D island growth mechanism with distinct nucleation and cluster growth regions before coalescence of a complete encapsulation layer with a thickness ⩾7 nm by 500 cycles. Encapsulated device performance testing further demonstrates that reducing ALD processing temperature to 100 °C minimizes OPV phase segregation and surface oxidation loss mechanisms as evidenced by improved short circuit current and fill factor retention when compared with the conventional 140–150 °C range. Ultra-thin AlO_x encapsulation by ALD provides significant device lifetime enhancement (∼30% device efficiency after 2000 h of air exposure), which is well beyond other ALD-based encapsulation works reported in the literature. Furthermore, the interfacial bonding strength at the OPV–AlO_x interface is shown to play a crucial role in determining film failure mode and therefore, directly impacts ultimate device lifetime.     

Study of the breakdown failure mechanisms for power AlGaN/GaN HEMTs implemented using a RF compatible process

The breakdown failure mechanisms for a family of power AlGaN/GaN HEMTs were studied. These devices were fabricated using a commercially available MMIC/RF technology with a semi-insulating SiC substrate. After a 10 min thermal annealing at 425 K, the transistors were subjected to temperature dependent electrical characteristics measurement. Breakdown degradation with a negative temperature coefficient of ?0.113 V/K for the devices without field plate was found. The breakdown voltage is also found to be a decreasing function of the gate length. Gate current increases simultaneously with the drain current during the drain-voltage stress test. This suggests that the probability of a direct leakage current path from gate to the 2-DEG region. The leakage current is attributed by a combination of native and generated traps/defects dominated gate tunneling, and hot electrons injected from the gate to channel. Devices with field plate show an improvement in breakdown voltage from ～40 V (with no field plate) to 138 V and with lower negative temperature coefficient. A temperature coefficient of ?0.065 V/K was observed for devices with a field plate length of 1.6 μm.