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1.
介绍了一种32位对数跳跃加法器结构.该结构采用ELM超前进位加法器代替进位跳跃结构中的组内串行加法器,同ELM相比节约了30%的硬件开销.面向该算法,重点对关键单元进行了晶体管级的电路设计.其中的进位结合结构利用Ling算法,采用支路线或电路结构对伪进位产生逻辑进行优化;求和逻辑的设计利用传输管结构,用一级逻辑门实现"与-民或"功能;1.0μm CMOS工世实现的32位对数跳跃加法器面积为0.62mm2,采用1μm和0.25μm 工世参数的关键路径延迟分别为6ns和0.8ns,在100MHz下功耗分别为23和5.2mW.  相似文献   

2.
贾嵩  刘飞  刘凌  陈中建  吉利久 《半导体学报》2003,24(11):1159-1165
介绍了一种32位对数跳跃加法器结构.该结构采用EL M超前进位加法器代替进位跳跃结构中的组内串行加法器,同EL M相比节约了30 %的硬件开销.面向该算法,重点对关键单元进行了晶体管级的电路设计.其中的进位结合结构利用L ing算法,采用支路线或电路结构对伪进位产生逻辑进行优化;求和逻辑的设计利用传输管结构,用一级逻辑门实现“与-异或”功能;1.0 μm CMOS工艺实现的32位对数跳跃加法器面积为0 .6 2 mm2 ,采用1μm和0 .2 5 μm工艺参数的关键路径延迟分别为6 ns和0 .8ns,在10 0 MHz下功耗分别为2 3和5 .2 m W.  相似文献   

3.
设计一个应用于高性能微处理器的快速64位超前进位对数加法器.通过分析超前进位对数加法器原理,提出了改进四进制Kogge-Stone树算法的64位超前进位对数加法器结构,并结合使用多米诺动态逻辑、时钟延迟多米诺逻辑和传输门逻辑等技术来设计和优化电路.该加法器采用SMIC 0.18 μm CMOS工艺实现,在最坏情况下完成一次加法运算时间为486.1 ps,与相同工艺和相同电路结构采用静态CMOS实现相比,大大减少了加法器各级门的延迟时间,取得良好的电路性能.  相似文献   

4.
通过对计算机加法器的研究,从门电路标准延迟模型出发,在对超前进位加法器逻辑公式研究的基础上,在主要考虑速度的前提下,给出了超前进位加法器的逻辑电路的设计方案。主要对16位、32位加法器的逻辑电路进行分析设计,通过计算加法器的延迟时间来对比超前进位加法器与传统串行进位链加法器,得出超前进位算法在实际电路中使加法器的运算速度达到最优。  相似文献   

5.
张爱华 《微电子学》2018,48(6):802-805
为了实现高性能的加法器,提出了面向功耗延迟积(PDP)优化的混合进位算法。该算法能快速搜索加法器的混合进位,以优化PDP。采用超前进位算法和行波进位算法交替混合,兼具超前进位算法速度快和行波进位算法功耗低的特点。该算法采用C语言实现并编译,结果应用于MCNC Benchmark电路,进行判定测试。与应用三种传统算法的加法器相比,应用该算法的加法器在位数为8位、16位、32位和64位时,PDP改进量分别为40.0%、70.6%、85.6%和92.9%。  相似文献   

6.
袁浩  唐建  方毅 《通信技术》2014,(3):339-342
在对超前加法器逻辑算法分析的基础上,介绍了一种优化设计方法。宽位加法器采用多层CLA( Carry Look-ahead Adder)块技术,按四位为一组进行组间超前进位,减小硬件延时,达到并行、高速的目的。并在晶体管级重点对全加器进行优化设计,从而降低整个电路的延时、面积和功耗。仿真结果表明,在SMIC65 nm工艺下,设计出的16位超前进位加法器,其延时,面积,功耗相比传统结构都有了明显的改善,达到了优化的效果。  相似文献   

7.
32位稀疏树加法器的设计改进与实现   总被引:1,自引:0,他引:1  
提出了一种改进进位运算的32位稀疏树加法器。在对现有稀疏树加法器使用的进位运算算子"o"进行深入探讨的基础上,对该算子的表达式做出了适当改进,去除了原算子中进位输入须为0的前提条件,同时保留了原算子适用于稀疏树进位结构的运算特性。采用该改进算子的32位稀疏树加法器可以并行地产生进位输入分别为0和1时的一对"和"输出,并可根据需要选择输出相应的结果。在1.2V130nm典型CMOS工艺条件下,经由HSPICE仿真,改进的32位稀疏树加法器的关键路径延迟为10.8FO4。结果表明,该加法器在运算能力得到扩充的同时,在运算速度方面也具有一定优势。  相似文献   

8.
为提高长加法器的运算速度,扩展操作位数,提出了一种加法器结构--混合模块顶层进位级联超前进位加法器(TC2CLA).该结构将层数Mi>1的CLA模块底层进位级联改为顶层超前进位单元进位级联.在CLA单元电路优化和门电路标准延迟时间tpd的基础上,由进位关键路径推导出混合模块TC2CLA的模块延迟时间公式,阐明了公式中各项的意义.作为特例,导得了相同模块TC2CLA的模块延迟时间公式.并得出和证明了按模块层数递增级联序列是混合模块TC2CLA各序列中延迟时间最短、资源(面积)占用与功耗不变的速度优化序列.这一结论成为优化设计的一个设计规则.还给出了混合模块级联序列数的公式和应用实例.TC2CLA和CLA的延迟时间公式表明,在相同模块序列和不等待(组)生成、传输信号的条件下,最高位进位延迟时间及最高位和的最大延迟时间减小.  相似文献   

9.
超前进位加法器混合模块延迟公式及优化序列   总被引:4,自引:2,他引:2  
为扩展操作位数提出了一种更具普遍性的长加法器结构——混合模块级联超前进位加法器。在超前进位加法器(CLA)单元电路优化和门电路标准延迟模型的基础上,由进位关键路径推导出混合模块级联CLA的模块延迟时间公式,阐明了公式中各项的意义。作为特例,自然地导出了相同模块级联CLA的模块延迟时间公式。并得出和证明了按模块层数递增级联序列是混合模块级联CLA各序列中延迟时间最短、资源(面积)占用与功耗不变的速度优化序列。这一结论成为优化设计的一个设计规则。还给出了级联序列数的公式和应用实例。  相似文献   

10.
混合模块无等待时间序列超前进位加法器设计   总被引:1,自引:1,他引:0  
在不增加超前进位加法器模块延迟时间的条件下,为最大限度地扩展操作位数,在分析混合模块超前进位加法器(CLA)延迟时间公式的基础上提出了混合模块无等待时间序列超前进位加法器.给出了混合模块CLA的无等待时间序列和无等待时间完全序列的定义,推证出序列的延迟时间公式及重要性质.并在功耗、面积(资源)占用约束下,优化设计了操作位数复盖范围为10~854位的94个混合模块无等待时间序列超前进位加法器.实现了保持CLA模块速度条件下,最大限度地扩展操作位数的目的.  相似文献   

11.
A CMOS arithmetic logic unit is presented with a minimum number of transistors and high speed arithmetic operations. Multiple carry chain adders and a novel 1 bit adder, are used in a carry select adder. The carry chain adder has a high degree of shared gates with a low propagation delay  相似文献   

12.
Resonant tunneling devices and circuit architectures based on monostable-bistable transition logic elements (MOBILEs) are promising candidates for future nanoscale integration. In this paper, the design of clocked MOBILE-type threshold logic gates and their application to arithmetic circuit components is investigated. The gates are composed of monolithically integrated resonant tunneling diodes and heterostructure field-effect transistors. Experimental results are presented for a programmable NAND/NOR gate. Design related aspects such as the impact of lateral device scaling on the circuit performance and a bit-level pipelined operation using a four phase clocking scheme are discussed. The increased computational functionality of threshold logic gates is exploited in two full adder designs having a minimal logic depth of two circuit stages. Due to the self-latching behavior the adder designs are ideally suited for an application in a bit-level pipelined ripple carry adder. To improve the speed a novel pipelined carry lookahead addition scheme for this logic family is proposed  相似文献   

13.
An efficient charge recovery logic circuit   总被引:1,自引:0,他引:1  
Efficient charge recovery logic (ECRL) is proposed as a candidate for low-energy adiabatic logic circuit. Power comparison with other logic circuits is performed on an inverter chain and a carry lookahead adder (CLA). ECRL CLA is designed as a pipelined structure for obtaining the same throughput as a conventional static CMOS CLA. Proposed logic shows four to six times power reduction with a practical loading and operation frequency range. An inductor-based supply clock generation circuit is proposed. Circuits are designed using 1.0-μm CMOS technology with a reduced threshold voltage of 0.2 V  相似文献   

14.
Using an enhanced multiple output domino logic (EMODL) implementation of a carry lookahead adder (CLA), sums of several consecutive bits can be built in one nFET tree with a single carry-in. Based on this result, a new sparse carry chain architecture is proposed for the CLA adder. We demonstrate the design approach using a 32-b adder, and show that only four carries are sufficient for generating all sums, with a consequent reduction in the number of stage delays. Using a 1.2-μm CMOS technology, we verify our simulation procedures by fabrication and measurement of a 2.7 ns critical path  相似文献   

15.
The efficient implementation of adders in differential logic can be carried out using a new generate signal (N) presented in this paper. This signal enables iterative shared transistor structures to be built with a better speed/area performance than a conventional implementation. It also allows adders developed in domino logic to be easily adapted to differential logic. Based on this signal, three 32-b adders in differential cascode switch voltage (DCVS) logic with completion circuit for applications in self-timed circuits have been fabricated in a standard 1.0-μm two-level metal CMOS technology. The adders are: a ripple-carry (RC) adder, a carry look-ahead (CLA) adder, and a binary carry look-ahead (BCL) adder. The RC adder has the best levels of performance for random input data, but its delay is significantly influenced by the length of the carry propagation path, and thus is not recommended in circuits with nonrandom input operands. The BCL adder is the fastest but has a high cost in chip area. The CLA adder provides an intermediate option, with an area which is 20% greater than that of the RC adder. Its average delay is slightly greater than that of the other two adders, with an addition time which increases slowly with the carry propagate length even for adders with a high number of bits  相似文献   

16.
先行进位光学并行多位全加器的研究   总被引:1,自引:0,他引:1  
陈历学  胡强生  吕其昌 《中国激光》1990,17(11):672-676
将二进制数的先行进位全加器的逻辑操作引入到光计算中,提出了用光学并行处理方法实现先行进位全加器逻辑操作的建议。信号以空间阵列方式编码,利用空间逻辑阵列,实现并行逻辑操作。研究了PD-LED的光电混合逻辑操作,利用PD—LED逻辑器件,从实验上验证了先行进位光学并行多位全加器,获得了满意的结果。  相似文献   

17.
Ruiz  G.A. 《Electronics letters》1996,32(17):1556-1557
A four-bit carry look-ahead (CLA) CMOS adder based on transistor sharing in a multi-output differential cascode voltage switch (MODCVS) logic is presented. This adder uses a new enhanced CLA unit, which enables the generation of all output carries in one single compact gate structure. Simulation results using HSPICE with CMOS 1.0 μm technology designs show that the four-bit adder proposed has 15.7% less transistors, 27.2% less silicon area, ~14% speed improvement, and a 29.1% reduction in average power consumption compared to a standard DCVS implementation  相似文献   

18.
For the realization of digital filters in a semicustom environment, high-performance adder and multiplier modules have been developed. These modules define the performance limits for digital finite impulse response (FIR) filters. The Gate Forest semicustom environment is a sea-of-gates-type transistor array. It supports the implementation of dynamic (domino) CMOS logic circuits. The circuit-design technique is applicable to compact high-speed designs. The realized dynamic adder architecture consists of a 2-b group adder and a Manchester carry chain (MCC). For an N-b addition this results in a N/2-b carry lookahead path. This dynamic adder scheme can be expanded into 4-b group adder modules. The multiplier module is a combination of a modified Booth-coded static adder array with a final dynamic MCC adder. The multiplier is clocked with a single (symmetric) clock signal. The clock signal is divided into a precharge pulse, in which the static part of the multiplier added array is evaluated, and an evaluation phase for the generation of the multiplication result (least significant bits). A 16-b×16-b multiplier based on this architecture runs with a 40-MHz system clock. The first chips have been processed in a 2-μm CMOS double-metal technology  相似文献   

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