Unpassivated GaN/AlGaN/GaN power high electron mobility transistors with dispersion controlled by epitaxial layer design

In this paper, a novel GaN/AlGaN/GaN high electron mobility transistor (HEMT) is discussed. The device uses a thick GaN-cap layer (∼250 nm) to reduce the effect of surface potential fluctuations on device performance. Devices without Si₃N₄ passivation showed no dispersion with 200-ns-pulse-width gate-lag measurements. Saturated output-power density of 3.4 W/mm and peak power-added efficiency (PAE) of 32% at 10 GHz (V_DS=+15 V) were achieved from unpassivated devices on sapphire substrates. Large gate-leakage current and low breakdown voltage prevented higher drain-bias operation and are currently under investigation.     

Defects in molecular beam epitaxial GaAs grown at low temperatures

We have utilized a variable energy positron beam and infrared transmission spectroscopy to study defects in GaAs epilayers grown at low temperatures (LT-GaAs) by molecular beam epitaxy. We have measured the Doppler broadening of the positron-electron annihilation gamma ray spectra as a function of positron implantation energy. From these measurements, we have obtained results for the depth profiles of Ga monovacancies in unannealed LT-GaAs and Ga monovacancies and arsenic cluster related defects in annealed LT-GaAs. We have also studied the effects of the Si impurities in annealed LT-GaAs. The infrared transmission measurements on unannealed LT-GaAs furnish a broad defect band, related to As antisites, centered at 0.370 eV below the conduction band.     

Restraints in low dimensional organic semiconductor devices at high current densities

The understanding of the charge carrier transport in electronic materials is of crucial interest for the design of efficient devices including especially the restraints that arise from device miniaturization. In this work the performance of organic thin-film and single crystal field-effect transistors with the same active material was studied in detail focusing on the high current density regime, where a pronounced non-hysteretic maximum in the transconductance was found. Interestingly, in this operation mode for both, thin films and single crystals, comparable densities of free and gate-induced charge carriers were estimated. Kelvin probe microscopy was used to measure the contact potential difference and the electrical field along the transistor channel during device operation exhibiting the formation of local space charges in the high current density regime.     

A CNFET-based hybrid multi-threshold 1-bit full adder design for energy efficient low power applications

In this article, a low-power and energy-efficient hybrid full adder circuit is proposed, which is implemented based on multi-threshold NAND and NOR gates and transmission gate multiplexers. In order to implement this circuit, carbon nano tube field effect transistors are utilised. For evaluating the proposed design, comprehensive simulations are performed with regard to the most important aspects power, delay and power-delay product. The results are presented and displayed the superiority of the proposed cell in different voltage levels, load conditions, temperatures and robustness against process variations.     

阻抗变换夹具在大功率负载牵引测试中的应用

为了实现对大功率RF LDMOS晶体管的精确测试,提出了一种应用切比雪夫阻抗变换夹具进行负载牵引测试的方法。这种方法通过将阻抗变换夹具的 S 参数在负载牵引系统中去嵌入,使得测试端面的特性阻抗从传统的50Ω变换到10Ω,扩大了系统的测试范围,能准确有效地完成大功率负载牵引测试。实际测试飞思卡尔公司的AFT09S282N的结果表明,该方法达到了预期效果。     

Properties of spin-on glass as an insulator for InP metal-insulator-semiconductor structures

The application of Futurrex IC1-200 spin-on glass as an insulator for InP metal-insu-lator-semiconductor (MIS) structures including InP MIS capacitors and InP MIS field-effect transistors (MISFET’s) was investigated. Preliminary measurements of the elec-trical properties of the spin-on glass were performed using Si MIS structures with the spin-on glass insulator layer. It was found that the spin-on glass which is subjected to a final curing treatment utilizing a rapid-thermal annealing at 600° C for 5 sec in a O₂ ambient exhibits the best electrical properties. However, it was demonstrated by sec-ondary ion mass spectroscopy that when done on InP, the 600° C rapid-thermal an-nealing resulted in the outdiffusion of indium and phosphorus into the spin-on glass. The change in the spin-on glass electrical characteristics due to this outdiffusion re-sulted in an instability in the InP MISFET operation.     

A beam steering antenna for X-band high power applications

There is a considerable interest in the antennas which have high power handling capacity with beam steering functionality. The design of narrow side waveguide slot-array antenna for high power applications is introduced in this paper. An approach to achieve a uniform radiation slot waveguide antenna is presented. The large scale array antenna can be composed of such antenna cells. Moreover, it is possible to realize beam steering in the azimuth direction by adjusting the broad wall dimension of the waveguide. Besides, this slot waveguide antenna is expected to have high power handling capacity in vacuum environment, because there is no dielectric or electric field enhancement inside the antenna.     

3.5GHz 65W硅脉冲大功率晶体管研制

介绍了采用梳状发射极自对准工艺研制的硅微波脉冲大功率晶体管的实验结果。在3．5GHz频率下,该晶体管脉冲输出功率65W,功率增益7dB,集电极效率35％（脉冲宽度100微秒,占空比5％）。     

Floorplanning for low power IC design considering temperature variations

Non-uniformity in thermal profiles of integrated circuits (ICs) is an issue that threatens their performance and reliability. This paper investigates the correlation between the total power consumption and the temperature variations across a chip. As a result, floorplanning guidelines are proposed that uses the correlation to efficiently optimize the chip's total power and takes into account the thermal uniformity. It is demonstrated that optimizing a floorplan to minimize either the leakage or the peak temperature can lead to a significant increase in the total power consumption. In this paper, the experimental results show that lowering the temperature variations across a chip not only addresses performance degradation and reliability concerns, but also significantly contributes to chip power reduction. In addition, it is found that although uniformity in the thermal profile can be very effective in lowering the total power consumption, the most uniform temperature distribution does not necessarily correspond to the highest power savings. Consequently, for some applications, a 2% deviation from the minimum total power is traded for up to a 25% increase in thermal uniformity. The presented method is implemented for an Alpha 21264 processor running Spec 2000 benchmarks.     

Failure rate calculation method for high power devices in space applications at low earth orbit

This paper discusses the universal calculation method for space proton induced failure rate on high power device. High energetic particles can be the reason of power device failure in both terrestrial and space. T-CAD simulation result gives a threshold charge value for the device destruction which is triggered by energetic proton from space. The amount of threshold charge depends on applied voltage for high power device. The probability of charge generation in silicon due to proton penetration is considered as well. This probability function variation depends on the thickness of device and incident energy of proton which studied before at there. Last consideration on this paper is 3.3 kV PiN diode's Single Event Upset Cross section and failure rate which was calculated by proposed method in Low earth orbit environment condition.     

Optimization of selective area growth of GaAs by low pressure organometallic vapor phase epitaxy for monolithic integrated circuits

GaAs MESFET device structures have been grown on silicon nitride or silicon dioxide masked 50 and 76 mm GaAs substrates by low pressure organometallic vapor phase epitaxy. Very smooth, featureless morphology and 100 percent selectivity of GaAs islands have been achieved over a range of growth conditions. Optimization of the GaAs p-buffer of the field effect transistor structure has led to improved device performance, including increased breakdown voltage. Device characteristics of the 0.5 μm gate low noise metal semiconductor field-effect transistors fabricated on these islands show good performance and wafer to wafer reproducibility on the second device lot.     

Comprehensive review of high power factor ac-dc boost converters for PFC applications

High power factor rectifiers have been consolidated as an effective solution to improve power quality indices in terms of input power factor correction, reduction in the total harmonic distortion of the input current and also regulated dc voltages. Within this context, this subject has motivated the introduction of numerous converter topologies based on classic dc-dc structures associated with novel control techniques, thus leading to the manufacturing of dedicated integrated circuits that allow high input power factor by adding a front-end stage to switch-mode converters. In particular, boost converters in continuous current mode (CCM) are widely employed since they allow obtaining minimised electromagnetic interference levels. This work is concerned with a literature review involving relevant ac-dc single-phase boost-based topologies with high input power factor. The evolution of aspects regarding the conventional boost converter is shown in terms of improved characteristics inherent to other ac-dc boost converters. Additionally, the work intends to be a fast and concise reference to single-phase ac-dc boost converters operating in CCM for engineers, researchers and experts in the field of power electronics by properly analysing and comparing the aforementioned rectifiers.     

Flexible air-stable three-dimensional polymer field-effect transistors with high output current density

Flexible air-stable short-channel polymer organic field-effect transistor (OFET) arrays with high saturated output current density are demonstrated by utilizing a novel solution-processed naphthobisthiadiazole (NTz) based donor–acceptor semiconducting polymer (PNTz4T) and designing a three-dimensional vertical channel structure with an extremely large ratio of channel width to channel length. The saturated mean field-effect mobility of 0.16 cm²/V s of the short-channel polymer devices remains over one month resulting in air-stable OFET arrays with high on/off ratio over 10⁶ and powerful current–density exceeding 0.3 A/cm² under low operation voltage, both of which meet the requirements for such applications as driving organic light-emitting diodes in active-matrix displays.     

Improvement for low power high performance hybrid type CAM

Based on the analysis of typical hybrid-type content addressable memory （CAM） structures, a hybrid-type CAM architecture with lower power consumption and higher stability was proposed. This design changes the connection of a N-type metal-oxide-semiconductor （NMOS） transistor in the control circuit, which greatly reduces the power consumption during comparison by making the match line simply discharge to the NMOS threshold voltage. A comparative study was made between conventional and the proposed hybrid-type CAM architecture by semiconductor manufacturing international corporation （SMIC） 65 nm complementary metal-oxide-semiconductor （CMOS） technology. Simulation shows that the power consumption of the proposed structure is reduced by 23%. Furthermore, the proposed design also adjusts the match line （ML） discharge path. In case that, the not and type （NAND-type） block is matched and the not or type （NOR-type） block is mismatched, the jitter voltage on the match line can be decreased largely.     

Threshold voltage degradation under high Vgs and low Vds on 200 V SOI power devices

The hot-carrier degradation behavior of the 200 V lateral insulated gate bipolar transistor and lateral diffused MOS transistor both on SOI substrates (SOI-LIGBT and SOI-LDMOS) under high Vgs and low Vds is experimentally investigated. It is shown that the hot electron injection and trapping into gate oxide in the channel region will domains the degradation, which results in the positive threshold voltage (Vth) shift, however, it is very interesting that the degradation level in SOI-LIGBT device is much more serious than that in SOI-LDMOS device. Finally, an improved method to reduce the Vth degradation of SOI-LIGBT is also presented, which is adding a P-type buried layer under the source to change the hole current path. All the results have been verified by MEDICI simulations.     

The novel SCR-based ESD protection with low triggering and high holding voltages

This paper introduces a novel silicon controlled rectifier (SCR)-based circuit. The proposed device using 70 nm DRAM process obtained the high holding and low triggering voltages by using variable IR drop. These characteristics enable to discharge electrostatic discharge (ESD) current and ensure latch-up immunity for normal operations. Also, the proposed scheme is easily implemented through the modification of the metal connection compare to the conventional SCR-based device. We investigated electrical characteristics by both measurements and TCAD simulations. Measurement results showed the proposed SCR had triggering voltage of 6.2 V, holding voltage of 3.3 V, and the second breakdown current of 58 mA/μm.     

Large plate-like organic crystals from direct spin-coating for solution-processed field-effect transistor arrays with high uniformity

Solution-processed organic crystals are important in field-effect transistors because of their highly ordered molecular packing and ease of device fabrication. For practical applications, the patterning of organic crystal transistor arrays is critical. However, uniformity, which concerns the variation in electrical performance among devices fabricated simultaneously on the same substrate, is a common consideration in the commercial applications of the solution-processed organic crystal transistor arrays. Here, a simple approach for fabricating field-effect transistor arrays based on organic plate-like crystals is reported. Through this method, a direct spin-coating process from a mixture solution of organic semiconductor and polymer dielectric can produce organic plate-like crystals. The grain size of the crystals is observed to be hundreds of micrometers. By controlling the concentrations of the active materials, the transistor arrays exhibit high uniformity and good device performance. The results presented in this work promise that this approach is a comparable technology to hydrogenated amorphous silicon-based FETs and is a great candidate for practical applications in electronic devices.     

SiC field-effect devices operating at high temperature

Field-effect devices based on SiC metal-oxide-semiconductor (MOS) structures are attractive for electronic and sensing applications above 250°C. The MOS device operation in chemically corrosive, high-temperature environments places stringent demands on the stability of the insulating dielectric and the constituent interfaces within the structure. The primary mode of oxide breakdown under these conditions is attributed to electron injection from the substrate. The reliability of n-type SiC MOS devices was investigated by monitoring the gate-leakage current as a function of temperature. We find current densities below 17 nA/cm² and 3 nA/cm² at electric field strengths up to 0.6 MV/cm and temperatures of 330°C and 180°C, respectively. These are promising results for high-temperature operation, because the optimum bias point for SiC MOS gas sensors in near midgap, where the field across the oxide is small. Our results are valid for n-type SiC MOS sensors in general and have been observed in both the 4H and 6H polytypes.     

Organic field-effect transistor with extended indium tin oxide gate structure for selective pH sensing

In this study, organic field-effect transistors (OFETs) with extended gate structure were fabricated for selective pH sensing applications. Indium tin oxide (ITO) was used as extended gate electrode as well as an active layer for H⁺ sensing. The threshold voltage of the fabricated ion-selective OFET was varied by the changes in the electrochemical potential at the ITO electrode surface upon its exposure to buffer solutions with variable pH values. The sensor showed excellent linearity and a high sensitivity of 57–59 mV/pH in the pH range of 2–12. The selectivity of the ITO sensing layer to H⁺ ions was also investigated by measuring the interfering effect of Ca²⁺ and K⁺ ions in the buffer pH solutions. The results showed that the Ca²⁺ and K⁺ ions weakly interfere with the selective pH sensing of the ITO-extended gate OFET sensor device.