Ferroelectric transistor memory arrays on flexible foils

In this paper, we successfully fabricated and operated passive matrix P(VDF–TrFE) transistor arrays, i.e. memory arrays in which no pass-transistors or other additional electronic components are used. Because of the smaller cell, a higher integration density is possible. We demonstrate arrays up to a size of 16 × 16, processed on thin (25 μm) poly(ethylene naphthalate) substrates, using Indium–Gallium–Zinc–Oxide (IGZO) as the semiconductor and 200 nm-thick P(VDF–TrFE) as a ferroelectric gate dielectric. The memory transistors have remnant current modulations of ～10⁵ with a retention time of more than 12 days. They can be switched in less than 1 μs at operating voltages of 25 V. Switching speed is strongly decreased with decreasing voltage: at ～10 V the transistors do not switch within 10 s. This difference in switching speed of more than 4 orders in magnitude when changing the electric field by a factor of only 2.5 makes these memories robust towards disturb voltages, and forms the basis of integration of these transistors in passive matrix-addressable transistor arrays that contains only one (memory) transistor per cell. It is shown that with current technology and memory characteristics it is possible to scale up the array size in the future.     

A new MNOS memory element—the tunnel diode

MNOS (Metal-Nitride-Oxide-Silicon) memory devices commercially available today consist of transistor arrays where each device represents a memory bit. Typical devices have densities greater than 8 K bits and are generally manufactured on epitaxial based processes for isolation. The state of each bit is determined by its threshold voltage and is sensed by interpreting if the transistor is in the “off” or “on” condition. A new MNOS memory element is described where detection of junction tunnelling current is used as the sense mechanism. Substrate forms the “third” terminal and the element has the possibility of being the basis of a dense array. The technique can be developed in p or n channel and can be used as an add-on to volatile random access memories.     

A single transistor electrically alterable cell

A novel single transistor electrically alterable memory cell is presented. The cell is based on floating gate technology using a double diffused (DMOS) transistor. Writing into the cell is achieved through hot electron injection while erasing is performed via Fowler-Nordheim tunneling through a thin oxide (100-Å) region. The memory cell requires only one transistor because the write and erase voltages range between 15-20 and 25-30 V, respectively. The writeability of the cell is enhanced by the thin oxide region and dependent on the proximity of this region to the channel of the DMOS transistor.     

A floating-gate MOS learning array with locally computed weightupdates

We have demonstrated on-chip learning in an array of floating-gate MOS synapse transistors. The array comprises one synapse transistor at each node, and normalization circuitry at the row boundaries. The array computes the inner product of a column input vector and a stored weight matrix. The weights are stored as floating-gate charge; they are nonvolatile, but can increase when we apply a row-learn signal. The input and learn signals are digital pulses; column input pulses that are coincident with row-learn pulses cause weight increases at selected synapses. The normalization circuitry forces row synapses to compete for floating-gate charge, bounding the weight values. The array simultaneously exhibits fast computation and slow adaptation: The inner product computes in 10 μs, whereas the weight normalization takes minutes to hours     

Enhancing Memory Window Efficiency of Ferroelectric Transistor for Neuromorphic Computing via Two-Dimensional Materials Integration

In-memory computing, particularly neuromorphic computing, has emerged as a promising solution to overcome the energy and time-consuming challenges associated with the von Neumann architecture. The ferroelectric field-effect transistor (FeFET) technology, with its fast and energy-efficient switching and nonvolatile memory, is a potential candidate for enabling both computing and memory within a single transistor. In this study,  the capabilities of an integrated ferroelectric HfO₂ and 2D MoS₂ channel FeFET in achieving high-performance 4-bit per cell memory with low variation and power consumption synapses, while retaining the ability to implement diverse learning rules, are demonstrated. Notably, this device accurately recognizes MNIST handwritten digits with over 94% accuracy using online training mode. These results highlight the potential of FeFET-based in-memory computing for future neuromorphic computing applications.     

基于肖特基栅共振隧穿三极管的器件模拟与实验分析

通过流片,制作出肖特基栅共振隧穿三极管(SGRTT).根据ATLAS软件的模拟发现,当发射极接地, 集电极接外加偏压时,栅极电压对于SGRTT的电流起到明显的控制作用.当集电极接地,栅极电压会主要影响峰值电压,其原因是栅极电压和发射极、集电极的电场分布将会改变耗尽区的分布.实验测试结果对这种现象也予以证实.     

基于肖特基栅共振隧穿三极管的器件模拟与实验分析

通过流片,制作出肖特基栅共振隧穿三极管（SGRTT） .根据ATLAS软件的模拟发现,当发射极接地,集电极接外加偏压时,栅极电压对于SGRTT的电流起到明显的控制作用.当集电极接地,栅极电压会主要影响峰值电压,其原因是栅极电压和发射极、集电极的电场分布将会改变耗尽区的分布.实验测试结果对这种现象也予以证实.     

Floating-gate nanofibrous electret arrays for high performance nonvolatile organic transistor memory devices

Nanofibrous electret arrays based organic field-effect floating-gate transistor memory was firstly developed by electrospinning. The nanofiber arrays are composed of a novel porphyrin molecule of [5,15-bis[4-(pyridyl)ethynyl]-10,20-diphenyl]-21H,23H-porphyrin (DPP) as charge-trapping elements and polystyrene (PS) as the tunneling layer. The floating-gate transistor memory based on electrospinning nanofibrous electret arrays exhibited a reliable controllable threshold voltage shift and effective charge-trapping ability which was obviously superior to the counterparts fabricated with widely employed spin-coating technique. The result shows that electrospinning can be used as an effective artificial strategy to produce predesigned microstructure for the electrets, optimize the electrical memory characteristics, and may be applied in future nonwoven electronic memory devices.     

Direct tunneling gate current model for symmetric double gate junctionless transistor with SiO2/high-k gate stacked dielectric

A junctionless transistor is emerging as a most promising device for the future technology in the decananometer regime. To explore and exploit the behavior completely, the understanding of gate tunneling current is of great importance. In this paper we have explored the gate tunneling current of a double gate junctionless transistor(DGJLT) for the first time through an analytical model, to meet the future requirement of expected high-k gate dielectric material that could replace SiO₂. We therefore present the high-k gate stacked architecture of the DGJLT to minimize the gate tunneling current. This paper also demonstrates the impact of conduction band offset, workfunction difference and k-values on the tunneling current of the DGJLT.     

Printable Ferroelectric PVDF/PMMA Blend Films with Ultralow Roughness for Low Voltage Non‐Volatile Polymer Memory

Here, a facile route to fabricate thin ferroelectric poly(vinylidene fluoride) (PVDF)/poly(methylmethacrylate) (PMMA) blend films with very low surface roughness based on spin‐coating and subsequent melt‐quenching is described. Amorphous PMMA in a blend film effectively retards the rapid crystallization of PVDF upon quenching, giving rise to a thin and flat ferroelectric film with nanometer scale β‐type PVDF crystals. The still, flat interfaces of the blend film with metal electrode and/or an organic semi‐conducting channel layer enable fabrication of a highly reliable ferroelectric capacitor and transistor memory unit operating at voltages as low as 15 V. For instance, with a TIPS‐pentacene single crystal as an active semi‐conducting layer, a flexible ferroelectric field effect transistor shows a clockwise I–V hysteresis with a drain current bistability of 10³ and data retention time of more than 15 h at ±15 V gate voltage. Furthermore, the robust interfacial homogeneity of the ferroelectric film is highly beneficial for transfer printing in which arrays of metal/ferroelectric/metal micro‐capacitors are developed over a large area with well defined edge sharpness.