一种用于驻极体麦克风的CT-SC ∑-△调制器

传统的模拟麦克风由于自身抗干扰能力差,很难满足新一代音频系统对输入端的要求,文章提出了一种用于数字麦克风的CT-SC∑-△调制器技术,将CT积分器和SC积分器结合在一个∑-△调制器中,可以与驻极体麦克风进行无缝连接,能够将麦克风产生模拟信号直接转换成后续数字设计平台所需的数字信号.测试结果表明,CT-SC∑-△调制器动态范围达到88 dB,等效输入参考噪声为5 μV,正常工作功耗为540 μw,休眠模式下消耗电流不超过10μA;与传统模拟麦克风相比,CT-SC∑-△调制器构成的数字麦克风可以提供更好的信噪比、更高的集成度、更低的功耗和更强的抗干扰能力.     

一种用于数字麦克风的低功耗低电压LDO

数字麦克风具有抗干扰能力强、集成度高、易于使用等优点,用于对功耗、体积敏感的便携式设备.研究了用于数字麦克风的低压差线性稳压器(LDO),该LDO除了具有稳压功能,为系统提供稳定和确定的电压外,还能在时钟频率低于休眠频率时,使数字麦克风进入休眠状态.流片测试表明,LDO电压调节范围为1.6～3.5 V,休眠频率为40～60 kHz,芯片待机电流为9μA.     

数字麦克风前置放大器

FAN3850X系列数字麦克风前置放大器,包括16dB或19dB增益FAN3850A和具有温度补偿功能的15dB增益FAN3850T。     

一种新型低噪声麦克风前置放大器的设计

传声器集成电路将接收到的麦克风声音信号转换成电流信号,再由前置放大器放大成电压信号。通常,当声音信号很微弱时,放大器放大声音信号时也放大了噪声,造成被放大的声音信号的信噪比很低。对两种电路进行了仿真试验,比较了Claus前置放大器和Eduard CMOS前置放大器的噪声特点。采用0.18μm CMOS工艺进行仿真,分析了电路的噪声频谱密度,提出了一种改进型CMOS前置放大器,有效地改善了前置放大器的信噪比。     

驻极体传声器小型前置放大器的设计

传声器是一种将声信号转变为相应的电信号的电声换能器。驻极体传声器是一种用驻极体材料制造的新型传声器。由于驻极体传声器的输出阻抗很高不能直接与音频放大器相接,需要在传声器内接入一只输入阻抗极高的结型场效应三极管来进行阻抗变换。一些小型的驻极体传声器虽然可以将场效应管集成于传声器内部,但是价格高昂;而传统的前置放大器体积又过于庞大。针对此利用现有的技术条件,设计了一种体积小、成本低廉而性能优良的前置放大器。     

一种基于低压差线性稳压器的放大器设计

设计了一种静态电流约为0.6μA的运算跨导放大器电路,并已经成功地应用于一款超低静态电流的新一代低压差线性稳压器芯片中。此放大器的突出优点是与Foldback过流保护电路融合在一起,使得芯片不需要专门的限流模块,大大减少了器件与电流支路,极大地提高了电流利用率,实现了超低功耗。     

使用两种频率补偿技术的低压差稳压器设计（英文）

介绍了一款具有两种频率补偿技术的低压差(LDO)线性稳压器。在LDO误差放大器的设计中,同时采用嵌套密勒补偿技术和具有可变负载的动态密勒补偿技术,确保LDO在负载电流变化60mA范围内的稳定性。该LDO采用联华电子公司(UMC)0.11μm CMOS工艺实现,所设计的LDO输入电压1.5~3.3V,负载最大电流60mA,输出电压稳定在1.23V。芯片测试结果表明,当负载电流从1mA突变为60mA或者从60mA突变为1mA时,LDO的输出稳定时间小于30μs,且输出电压变化小于12mV。在3.3V的输入电压下,LDO的静态电流为50μA,且在满负载变化时输出电压的变化仅有18mV。     

数字麦克风的应用方案及系统功能分区技术

导言绝大部分音频应用方案都先将输入的音频信号转为数字信号,才进一步加以处理。由于真实世界的音频信号属于微小的模拟信号,因此系统的输入端需要执行两种截然不同的功能:预先将输入信号放大,然后进行模拟/数字转换。 美国国家半导体已成功开发一款集成电路,取代传统驻极体电容器麦克风(ECM)一向使用的接面场效应晶体管(JFET),令驻极体电容器麦克风可以输出全数字信号。     

一种高电源抑制比的LDO电路的设计

电源抑制比（PSRR）反映的是电路对电源噪声的敏感程度,在电源管理电路中是极为重要的性能指标。总是希望有高的电源抑制比来抑制电源噪声对电路的影响。低压差线性稳压（LDO）电路中这个指标尤为重要,本文将设计一款具有高电源抑制比的低压差线性稳压器。     

一种全集成的麦克风可编程增益放大器设计

针对麦克风应用,设计一种全集成、高精度的可编程放大器电路。该电路采用电容增益以及高通滤波器的设计方法,无须片外去耦合电容,实现可编程增益放大器的单片集成。可编程增益放大器电路采用SMIC 0.13μm 1P8M CMOS工艺实现。完成后仿真结果表明,在电源电压1 V,增益18 dB,输入信号频率2 kHz,峰峰值50 mV时,可编程增益放大器动态范围达到73 dB,总谐波失真64 dB,整体功耗206μW,满足麦克风全集成、高精度的应用需求。     

A 147-dB dynamic range electronic attenuator for audiometricapplications with on-chip 1-W power amplifier

This paper presents an integrated circuit for audiometric applications, which includes a linearly controlled exponential attenuator with 147 dB of dynamic range and a power amplifier capable of driving 8 V_pp on a 7-Ω resistive load. The required attenuation is achieved in the current domain by exploiting the exponential transfer characteristic of bipolar transistors. In order to achieve a temperature-independent attenuation, in spite of the temperature-dependent bipolar transistor I_C-V_BE relationship, we produce on-chip an attenuation control voltage proportional to the absolute temperature. The 24-mm² chip, fabricated in a 2-μm high-voltage CMOS process, achieves the required dynamic range with 80 dB of spurious-free dynamic range (excluding harmonics) and -57 dB of total harmonic distortion, consuming 33 mA from a ±5-V power supply     

A continuous-time sigma-delta modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth

This paper presents the design and experimental results of a continuous-time /spl Sigma//spl Delta/ modulator for ADSL applications. Multibit nonreturn-to-zero (NRZ) DAC pulse shaping is used to reduce clock jitter sensitivity. The nonzero excess loop delay problem in conventional continuous-time /spl Sigma//spl Delta/ modulators is solved by our proposed architecture. A prototype third-order continuous-time /spl Sigma//spl Delta/ modulator with 5-bit internal quantization was realized in a 0.5-/spl mu/m double-poly triple-metal CMOS technology, with a chip area of 2.4 /spl times/ 2.4 mm/sup 2/. Experimental results show that the modulator achieves 88-dB dynamic range, 84-dB SNR, and 83-dB SNDR over a 1.1-MHz signal bandwidth with an oversampling ratio of 16, while dissipating 62 mW from a 3.3-V supply.     

An oversampled multibit CMOS D/A converter for digital audio with115-dB dynamic range

The analog part of a current-mode CMOS 5-b bidirectional digital/analog (D/A) converter for digital audio with 115-dB dynamic range and -90-dB distortion at 128-times oversampling is presented. The application of a multibit noise shaping approach combined with a sign-magnitude decoding in an oversampled D/A converter not only increases the dynamic range of the converter but also reduces the intermodulation sensitivity. A dynamic self-calibration technique is used to obtain the required relative accuracy and absolute linearity of the current sources. No laser or external trimming techniques are required     

A multibit delta-sigma audio DAC with 120-dB dynamic range

A 24-bit 192-kHz sample-rate digital-to-analog converter (DAC) achieves 120-dB A-weighted dynamic range in the 20-kHz band, and consumes 310 mW with a 5-V power supply. A third-order five-bit ΔΣ architecture optimized for high-end consumer audio has been developed and used. A switched-capacitor (SC) DAC combined with infinite-impulse response (IIR) and finite-impulse response (FIR) filters is employed to increase immunity to clock jitter, and reduce analog power. Partial-range dynamic element matching (DEM) enhances mismatch shaping with reduced circuit overhead. The 7.8-mm² chip fabricated in 0.5-μ m CMOS integrates a stereo DAC and all functions required for DVD-audio playback     

A 60-dB dynamic range two-stage RMS power detector

Analog Integrated Circuits and Signal Processing - This study presents a true root-mean-square (RMS) power detector with a wide dynamic range in a 180-nm BiCMOS process. An RMS power detector based...     

A 5-mW sigma-delta modulator with 84-dB dynamic range for GSM/EDGE

A sigma-delta modulator designed as part of a complete GSM/EDGE (enhanced data rate for GSM evolution) transceiver is described. High-resolution wide-band analog-to-digital converters enable the receiver to rely on digital processing, rather than analog filtering, to extract the desired signal from blocking channels. High linearity and low power consumption are the most stringent requirements for the converters in this wireless application. A single-bit 2-2-cascaded modulator operating at 13 MHz has been adopted for high linearity and stability. Low-power low-voltage techniques have been applied along with a top-down design approach in order to minimize the power dissipation. The ΣΔ modulator achieves 13.5 bits of resolution over a bandwidth of 180 kHz while dissipating 5 mW from 1.8-V and 2.4-V supplies. The circuit has been implemented in the CMOS portion of a 0.4-μm (drawn) BiCMOS technology and occupies an active area of 0.4 mm²     

A single-stage variable-gain amplifier with 70-dB dynamic range for CDMA2000 transmit applications

A variable-gain amplifier (VGA) circuit is presented with a gain range of more than 70 dB in a single stage. Vertical stacking of multipliers in a single-stage VGA results in a considerable saving of power, which is a prime requirement in cellular systems. The gain-in-dB is a linear function of the control voltage and has excellent stability over temperature. The amplifier is a part of a code-division multiple access cellular transmit integrated circuit, and provides good linearity and noise characteristics over a wide range of IF frequencies. The circuit is fabricated in a 30-GHz f/sub t/ BiCMOS technology and consumes 8 mA at 2.7 V.     

A 2.7-V 11.8-mW baseband ADC with 72-dB dynamic range for GSMapplications

A receive baseband analog-to-digital converter (ADC) for a GSM cellular radio system is presented. Low voltage and low power techniques have been applied across many aspects of the design. The circuit consists of two second-order double-sampled semi-bilinear ΣΔ modulators followed by two 576-tap digital finite-impulse response (FIR) GSM-channel filters with offset calibration. The complete ADC achieves a dynamic range of 72 dB and dissipates 11.8 mW from a 2.7-V supply. The area is 1.6 mm² in a 0.5-μm n-well double-poly triple-metal CMOS process     

一种适用于中频接收机的具有75dB动态范围的100MHz带通$\Sigma \Delta$调制器

本文介绍了一款适用于中频接收机的四阶开关电容带通$\Sigma \Delta$调制器,采样频率为100MHz。为优化谐振器的性能,文中提出了考虑运算放大器非理想特性后谐振器的传输函数。本文设计的调制器采用0.13-um标准CMOS工艺,在25MHz附近200KHz信号带宽内测得的SNDR和DR分别为68dB和75dB。调制器工作在1.2V电源电压下,总功耗为8.2mW。     

A 100-MHz bandpass sigma-delta modulator with a 75-dB dynamic range for IF receivers

A fourth-order switched-capacitor bandpassΣ△modulator is presented for digital intermediatefrequency (IF) receivers.The circuit operates at a sampling frequency of 100 MHz.The transfer function of the resonator considering nonidealities of the operational amplifier is proposed so as to optimize the performance of resonators.The modulator is implemented in a 0.13-μm standard CMOS process.The measurement shows that the signal-to-noise-and-distortion ratio and dynamic range achieve 68 dB and 75 dB,respectively,over a bandwidth of 200 kHz centered at 25 MHz,and the power dissipation is 8.2 mW at a 1.2 V supply.