共查询到20条相似文献,搜索用时 54 毫秒
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设计了一款适用于集成热真空传感器的二阶1位Σ-Δ调制器.该调制器采用前馈通道抑制积分器的输出摆幅、降低谐波失真、提高动态范围.为了降低运算放大器的1/f噪声,积分器中引入相关双采样电路.利用Matlab/Simulink,分析运算放大器的非理想性对调制器性能的影响.调制器由全差分开关电容电路实现.仿真结果表明:在4 MHz采样频率和6.8 kHz信号输入频率、-3 dBFS幅值下,电路的最大信噪比为86.9 dB,分辨率可达14位.调制器的有效面积为0.67 mm2.3 V电源电压供电时,功耗为12 mW,各项性能指标均满足设计要求. 相似文献
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设计了一款适用于集成热真空传感器的二阶1位Σ-Δ调制器。该调制器采用前馈通道抑制积分器的输出摆幅、降低谐波失真、提高动态范围。为了降低运算放大器的1/f噪声,积分器中引入相关双采样电路。利用Matlab/Simulink,分析运算放大器的非理想性对调制器性能的影响。调制器由全差分开关电容电路实现。仿真结果表明:在4 MHz采样频率和6.8 kHz信号输入频率-3、dBFS幅值下,电路的最大信噪比为86.9 dB,分辨率可达14位。调制器的有效面积为0.67 mm2。3 V电源电压供电时,功耗为12 mW,各项性能指标均满足设计要求。 相似文献
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设计了一种适用于过高磁场抗扰度的电容式隔离型全差分Σ-Δ调制器。它采用单环2阶1位量化的前馈积分器结构,运用斩波技术降低低频噪声和直流失调。与传统的全差分结构相比,该调制器的每级积分器均采用4个采样电容,在一个时钟周期内能实现两次采样与积分,所需的外部时钟频率仅为传统积分器的一半,降低了运放的压摆率及单位增益带宽的设计要求,实现了低功耗。基于CSMC 0.35 μm CMOS工艺,在5 V电源电压、10 MHz采样频率和256过采样率的条件下进行电路仿真。后仿真结果表明,调制器的SNDR为100.7 dB,THD为-104.9 dB,ENOB可达16.78位,总功耗仅为0.4 mA。 相似文献
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针对Σ-Δ调制器输入失调电压的需求,设计了一种新型低输入失调电压的Σ-Δ调制器。利用斩波稳定运算放大器和新颖的开关电容积分器,动态消除了直流失调电压以及低频噪声(主要包含1/f噪声),使得调制器的输入失调电压微乎其微。基于0.15 μm CMOS工艺,利用Hspice软件对电路进行仿真,同时采用Matlab和TCL对仿真结果进行分析。仿真结果表明,在电源电压为4.5~5.5 V、温度为-40 ℃~85 ℃、各种工艺角下,低频噪声抑制能力增加了15 dB,且当运算跨导放大器的失调电压为10 mV时,Σ-Δ调制器的输入失调电压由9.7 mV下降为0.4 mV。 相似文献
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A fourth-order switched-capacitor bandpassΣ△modulator is presented for digital intermediatefrequency (IF) receivers.The circuit operates at a sampling frequency of 100 MHz.The transfer function of the resonator considering nonidealities of the operational amplifier is proposed so as to optimize the performance of resonators.The modulator is implemented in a 0.13-μm standard CMOS process.The measurement shows that the signal-to-noise-and-distortion ratio and dynamic range achieve 68 dB and 75 dB,respectively,over a bandwidth of 200 kHz centered at 25 MHz,and the power dissipation is 8.2 mW at a 1.2 V supply. 相似文献
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Traditional feedforward structures suffer from performance constraints caused by the complex adder before quantizer.This paper presents an improved 4th-order 1 -bit sigma-delta modulator which has a simple adder and delayed input feedforward to relax timing constraints and implement low-distortion.The modulator was fabricated in a 0.35μm CMOS process,and it achieved 92.8 dB SNDR and 101 dB DR with a signal bandwidth of 100 kHz dissipating 8.6 mW power from a 3.3-V supply.The performance satisfies the requirements of a GSM system. 相似文献
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《半导体学报》2009,30(12)
A 1-V third order one-bit continuous-time (CT) ΣΔ modulator is presented. Designed in the SMIC mixed-signal 0.13-μm CMOS process, the modulator utilizes active RC integrators to implement the loop filter. An efficient circuit design methodology for the CT ΣΔ modulator is proposed and verified. Low power dissipation is achieved through the use of two-stage class A/AB amplifiers. The presented modulator achieves 81.4-dB SNDR and 85-dBdynamic range in a 20-kHz bandwidth with an over sampling ratio of 128. The total power consumption of the modulator is only 60μW from a 1-V power supply and the prototype occupies an active area of 0.12 mm~2. 相似文献
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A low-noise cascaded multi-bit sigma-delta pipeline analog-to-digital converter (ADC) with a low oversampling rate is presented. The architecture is composed of a 2-order 5-bit sigma-delta modulator and a cascaded 4-stage 12-bit pipelined ADC, and operates at a low 8X oversampling rate, The static and dynamic performances of the whole ADC can be improved by using dynamic element matching technique. The ADC operates at a 4 MHz clock rate and dissipates 300 mW at a 5 V/3 V analog/digital power supply. It is developed in a 0.35 μm CMOS process and achieves an SNR of 82 dB. 相似文献
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A low-noise cascaded multi-bit sigma-delta pipeline analog-to-digital converter (ADC) with a low over-sampling rate is presented. The architecture is composed of a 2-order 5-bit sigma-delta modulator and a cascaded 4-stage 12-bit pipelined ADC, and operates at a low 8X oversampling rate. The static and dynamic performances of the whole ADC can be improved by using dynamic element matching technique. The ADC operates at a 4 MHz clock rate and dissipates 300 mW at a 5 V/3 V analog/digital power supply. It is developed in a 0.35μm CMOS process and achieves an SNR of 82 dB. 相似文献
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Artur Silva Author Vitae Jorge Guilherme Author Vitae Nuno Horta Author Vitae 《Integration, the VLSI Journal》2009,42(1):34-46
A reconfigurable sigma-delta modulator, which is able to support the predictable standards for the fourth generation (4G) of mobile communication systems, is presented in this paper. This modulator was designed to cope with six different communications standards relying on a flexible architecture. Furthermore, the proposed architecture introduces the ability to process concurrently two different signals. The major design issues are outlined and operation modes are detailed. The feasibility of the presented solution is demonstrated using high-level system-level simulations as well as device-level simulations of the modulator implemented with switched capacitor circuits. 相似文献
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This paper introduces a low-noise low-cost ∑ △ modulator for digital audio analog-to-digital conversion.By adopting a low-noise large-output swing operation amplifier,not only is the flicker noise grea... 相似文献