用于单片集成热真空传感器的Σ-Δ调制器设计

设计了一款适用于集成热真空传感器的二阶1位Σ-Δ调制器.该调制器采用前馈通道抑制积分器的输出摆幅、降低谐波失真、提高动态范围.为了降低运算放大器的1/f噪声,积分器中引入相关双采样电路.利用Matlab/Simulink,分析运算放大器的非理想性对调制器性能的影响.调制器由全差分开关电容电路实现.仿真结果表明:在4 MHz采样频率和6.8 kHz信号输入频率、-3 dBFS幅值下,电路的最大信噪比为86.9 dB,分辨率可达14位.调制器的有效面积为0.67 mm2.3 V电源电压供电时,功耗为12 mW,各项性能指标均满足设计要求.     

用于单片集成热真空传感器的Σ-Δ调制器设计北大核心

设计了一款适用于集成热真空传感器的二阶1位Σ-Δ调制器。该调制器采用前馈通道抑制积分器的输出摆幅、降低谐波失真、提高动态范围。为了降低运算放大器的1/f噪声,积分器中引入相关双采样电路。利用Matlab/Simulink,分析运算放大器的非理想性对调制器性能的影响。调制器由全差分开关电容电路实现。仿真结果表明:在4 MHz采样频率和6.8 kHz信号输入频率-3、dBFS幅值下,电路的最大信噪比为86.9 dB,分辨率可达14位。调制器的有效面积为0.67 mm2。3 V电源电压供电时,功耗为12 mW,各项性能指标均满足设计要求。     

一种带斩波的双采样Σ-Δ调制器

设计了一种适用于过高磁场抗扰度的电容式隔离型全差分Σ-Δ调制器。它采用单环2阶1位量化的前馈积分器结构,运用斩波技术降低低频噪声和直流失调。与传统的全差分结构相比,该调制器的每级积分器均采用4个采样电容,在一个时钟周期内能实现两次采样与积分,所需的外部时钟频率仅为传统积分器的一半,降低了运放的压摆率及单位增益带宽的设计要求,实现了低功耗。基于CSMC 0.35 μm CMOS工艺,在5 V电源电压、10 MHz采样频率和256过采样率的条件下进行电路仿真。后仿真结果表明,调制器的SNDR为100.7 dB,THD为－104.9 dB,ENOB可达16.78位,总功耗仅为0.4 mA。     

一种用于音频DAC的可重构Σ-Δ调制器的设计

设计了一种适于嵌入式FPGA应用的可重构Σ-Δ调制器,并采用高效的流水线结构实现,它能够被设置为3阶或5阶,可支持不同字长(16-/18-/20-/24-位)PCM数据的满幅输入。通过Matlab仿真,针对16位、44.1 kHz、过采样率为128的输入信号,工作在三阶情况下的调制器可以获得超过100 dB的信噪比(SNR);而在输入为24位1、92 kHz、过采样率为32时,工作在5阶情况下的调制器的信噪比(SNR)超过了150 dB,很好地抑制了通带内的噪声。     

一种斩波稳定低噪声Σ-Δ调制器设计

针对Σ-Δ调制器输入失调电压的需求,设计了一种新型低输入失调电压的Σ-Δ调制器。利用斩波稳定运算放大器和新颖的开关电容积分器,动态消除了直流失调电压以及低频噪声(主要包含1/f噪声),使得调制器的输入失调电压微乎其微。基于0.15 μm CMOS工艺,利用Hspice软件对电路进行仿真,同时采用Matlab和TCL对仿真结果进行分析。仿真结果表明,在电源电压为4.5~5.5 V、温度为-40 ℃~85 ℃、各种工艺角下,低频噪声抑制能力增加了15 dB,且当运算跨导放大器的失调电压为10 mV时,Σ-Δ调制器的输入失调电压由9.7 mV下降为0.4 mV。     

一种高精度音频Σ-Δ调制器的研究

简要介绍了Σ-Δ调制器的基本原理,设计了一种适合数字音频应用的16位Σ-Δ调制器.该电路采用Chartered 0.5 μm标准CMOS工艺实现,工作电源电压为5 V,在工作频率为6.144 MHz、过采样率为128时,输入带内信噪比可达107 dB.     

一种低电压3阶4位前馈Σ-Δ调制器

介绍了一种应用于无线通信领域的低电压、带有前馈结构的3阶4位单环Σ-Δ调制器。为了降低Σ-Δ调制器的功耗,跨导放大器采用了带宽展宽技术。采用TSMC 0.13 μm CMOS工艺对电路进行仿真,仿真结果显示,当工作电压为1.2 V、采样频率为64 MHz、过采样比为16、信号带宽为2 MHz时,电路的SNDR达81 dB,功耗仅为7.78 mW。     

一种高精度音频Σ-Δ调制器的研究北大核心

介绍了Σ-Δ调制器的基本原理,设计了一种适合数字音频应用的16位Σ-Δ调制器。该电路采用Chartered 0.5μm标准CMOS工艺实现,工作电源电压为5V,在工作频率为6.144MHz、过采样率为128时,输入带内信噪比可达107dB。     

一种单环Δ-Σ调制器的全数字实现

针对无线人体局域网(WBAN),采用TSMC 0.18 μm CMOS工艺,对3阶单环结构Δ-Σ调制器进行了优化设计和全数字实现。实验结果表明,在Δ-Σ调制器中使用Qn方法实现对浮点小数的定点化,优化后的结构能够在运算精度、器件尺寸及功耗上达到平衡。该研究工作可以为实现全数字小数锁相环提供重要的理论及设计参考。     

一种单环Δ-Σ调制器的全数字实现

针对无线人体局域网(WBAN),采用TSMC 0.18μm CMOS工艺,对3阶单环结构Δ-Σ调制器进行了优化设计和全数字实现。实验结果表明,在Δ-Σ调制器中使用Qn方法实现对浮点小数的定点化,优化后的结构能够在运算精度、器件尺寸及功耗上达到平衡。该研究工作可以为实现全数字小数锁相环提供重要的理论及设计参考。     

A 100-MHz bandpass sigma-delta modulator with a 75-dB dynamic range for IF receivers

A fourth-order switched-capacitor bandpassΣ△modulator is presented for digital intermediatefrequency (IF) receivers.The circuit operates at a sampling frequency of 100 MHz.The transfer function of the resonator considering nonidealities of the operational amplifier is proposed so as to optimize the performance of resonators.The modulator is implemented in a 0.13-μm standard CMOS process.The measurement shows that the signal-to-noise-and-distortion ratio and dynamic range achieve 68 dB and 75 dB,respectively,over a bandwidth of 200 kHz centered at 25 MHz,and the power dissipation is 8.2 mW at a 1.2 V supply.     

改进的适用于GSM的单环过采样调制器

传统的前馈结构由于在量化器前存在复杂的加法器因而会造成性能受限。本文给出了一个改进的四阶一位过采样调制器, 它采用了简单的加法器和延时输入前馈通路,从而降低了调制器的时序需求同时实现低失真。调制器由0.35微米工艺流片,完成了92.8dB的信号噪声失真比和101dB的动态范围,信号带宽100kHz,在3.3V电源电压下,消耗8.6mW。本调制器的性能满足GSM系统的需求。     

An improved single-loop sigma-delta modulator for GSM applications

Traditional feedforward structures suffer from performance constraints caused by the complex adder before quantizer.This paper presents an improved 4th-order 1 -bit sigma-delta modulator which has a simple adder and delayed input feedforward to relax timing constraints and implement low-distortion.The modulator was fabricated in a 0.35μm CMOS process,and it achieved 92.8 dB SNDR and 101 dB DR with a signal bandwidth of 100 kHz dissipating 8.6 mW power from a 3.3-V supply.The performance satisfies the requirements of a GSM system.     

A 1-V 60-μW 85-dB dynamic range continuous-time third-order sigma-delta modulator

A 1-V third order one-bit continuous-time (CT) ΣΔ modulator is presented. Designed in the SMIC mixed-signal 0.13-μm CMOS process, the modulator utilizes active RC integrators to implement the loop filter. An efficient circuit design methodology for the CT ΣΔ modulator is proposed and verified. Low power dissipation is achieved through the use of two-stage class A/AB amplifiers. The presented modulator achieves 81.4-dB SNDR and 85-dBdynamic range in a 20-kHz bandwidth with an over sampling ratio of 128. The total power consumption of the modulator is only 60μW from a 1-V power supply and the prototype occupies an active area of 0.12 mm~2.     

一种适用于中频接收机的具有75dB动态范围的100MHz带通$\Sigma \Delta$调制器

本文介绍了一款适用于中频接收机的四阶开关电容带通$\Sigma \Delta$调制器,采样频率为100MHz。为优化谐振器的性能,文中提出了考虑运算放大器非理想特性后谐振器的传输函数。本文设计的调制器采用0.13-um标准CMOS工艺,在25MHz附近200KHz信号带宽内测得的SNDR和DR分别为68dB和75dB。调制器工作在1.2V电源电压下,总功耗为8.2mW。     

A 16-bit cascaded sigma-delta pipeline A/D converter

A low-noise cascaded multi-bit sigma-delta pipeline analog-to-digital converter (ADC) with a low oversampling rate is presented. The architecture is composed of a 2-order 5-bit sigma-delta modulator and a cascaded 4-stage 12-bit pipelined ADC, and operates at a low 8X oversampling rate, The static and dynamic performances of the whole ADC can be improved by using dynamic element matching technique. The ADC operates at a 4 MHz clock rate and dissipates 300 mW at a 5 V/3 V analog/digital power supply. It is developed in a 0.35 μm CMOS process and achieves an SNR of 82 dB.     

A 16-bit cascaded sigma-delta pipeline A/D converter

A low-noise cascaded multi-bit sigma-delta pipeline analog-to-digital converter （ADC） with a low over-sampling rate is presented. The architecture is composed of a 2-order 5-bit sigma-delta modulator and a cascaded 4-stage 12-bit pipelined ADC, and operates at a low 8X oversampling rate. The static and dynamic performances of the whole ADC can be improved by using dynamic element matching technique. The ADC operates at a 4 MHz clock rate and dissipates 300 mW at a 5 V/3 V analog/digital power supply. It is developed in a 0.35μm CMOS process and achieves an SNR of 82 dB.     

Reconfigurable multi-mode sigma-delta modulator for 4G mobile terminals

A reconfigurable sigma-delta modulator, which is able to support the predictable standards for the fourth generation (4G) of mobile communication systems, is presented in this paper. This modulator was designed to cope with six different communications standards relying on a flexible architecture. Furthermore, the proposed architecture introduces the ability to process concurrently two different signals. The major design issues are outlined and operation modes are detailed. The feasibility of the presented solution is demonstrated using high-level system-level simulations as well as device-level simulations of the modulator implemented with switched capacitor circuits.     

A 65-nm low-noise low-cost ∑ △ modulator for audio applications

This paper introduces a low-noise low-cost ∑ △ modulator for digital audio analog-to-digital conversion.By adopting a low-noise large-output swing operation amplifier,not only is the flicker noise grea...     

用于电池管理系统的Sigma-Delta ADC模型优化设计及研究

针对用于电池管理系统中数模转换器的高精度要求以及Sigma-Delta ADC的适用特点,提出了一种加入零点优化的单环三阶前馈调制器结构以及适用于本系统的低功耗数字滤波器模型,通过噪声传输函数设计三准则和信号频谱分析给出具体设计及仿真参数,经验证该模型达到系统所需16位有效分辨率要求且易于电路实现。