Low-Footprint Optical Interconnect on an SOI Chip Through Heterogeneous Integration of InP-Based Microdisk Lasers and Microdetectors

We present a proof-of-principle demonstration of a low-footprint optical interconnect on a silicon-on-insulator (SOI) chip. The optical link consists of a heterogeneously integrated, InP-based microdisk laser (MDL) and microdetector, coupled to a common SOI wire waveguide. Applying an electrical current to the MDL resulted in a detector current up to 1 $mu$A.      

An approach to the optical interconnect made in standard CMOS process

A standard CMOS optical interconnect is proposed, including an octagonal-annular emitter, a field oxide,metal 1-PSG/BPSG-metal 2 dual waveguide, and an ultra high-sensitivity optical receiver integrated with a fingered P/N-well/P-sub dual photodiode detector. The optical interconnect is implemented in a Chartered 3.3-V 0.35-μm standard analog CMOS process with two schemes for the research of the substrate noise coupling effect on the optical interconnect performance: with or without a GND-guardring around the emitter. The experiment results show that the optical interconnect can work at 100 kHz, and it is feasible to implement optical interconnects in standard CMOS processes.     

Polymer-Waveguide-Based Board-Level Optical Interconnect Technology for Datacom Applications

On the basis of a realized 12$,times,$ 10 Gb/s card-to-card optical link demonstrator, the capabilities of a polymer-waveguide-based board-level optical interconnect technology are presented. The conception and realization of the modular building blocks required for this board-level optical interconnect technology are described in detail. In particular, we report on the fabrication and characterization of board-integrated optical low-loss polymer waveguides that are compatible with printed circuit board (PCB) manufacturing processes. We also explain our fully passive alignment technique, superseding time-consuming active positioning of components and connectors. To realize optical transceiver modules comprising vertical cavity surface emitting laser (VCSEL) arrays with laser drivers and photodetector arrays with transimpedance amplifiers (TIAs), a mass-production concept based on wafer-level processing has been elaborated and successfully implemented.      

A 64-Mb embedded FRAM utilizing a 130-nm 5LM Cu/FSG logic process

A low-voltage (1.3 V) 64-Mb ferroelectric random access memory (FRAM) using a one-transistor one-capacitor (1T1C) cell has been fabricated using a state-of-the-art 130-nm transistor and a five-level Cu/flouro-silicate glass (FSG) interconnect process. Only two additional masks are required for integration of the ferroelectric module into a single-gate-oxide low-voltage logic process. Novel overwrite sense amplifier and programmable ferroelectric reference generation schemes are employed for fast reliable read-write cycle operation. Address access time for the memory is less than 30 ns while consuming less than 0.8 mW/MHz at 1.37 V. An embedded FRAM (eFRAM) density of 1.13 Mb/mm/sup 2/ is achieved with a cell size of 0.54 /spl mu/m/sup 2/ and capacitor size of 0.25 /spl mu/m/sup 2/.     

Effect of interconnect layer on Pb(Zr,Ti)O3 thin filmcapacitor degradation

Ferroelectric properties of a Pb(Zr,Ti)O₃ (PZT) thin film capacitor with a conventional Al/TiN/Ti interconnect layer are seriously degraded by annealing at around 400°C. The degradation is observed even if a contact hole on the top electrode is not formed. This indicates that the cause of the degradation is not the diffusion of the interconnect material into the PZT film, and this is confirmed by secondary ion mass spectrometry. We suggest that it is the thermal strain of the interconnect layer which imposes tensile stress on the PZT film during the annealing that degrades the ferroelectric properties of the PZT capacitor     

Channel cross-coupling in a polymer-based single-mode bus array

In this paper, a crosstalk model is developed to study the packing density and interconnect distance limitations of an optical interconnect system employing polymer-based single-mode bus arrays. The upper limit of channel packing density (1250 channels/cm at interconnect distance of 5 cm) is determined for the first time using the crosstalk model, in which channel cross-coupling among an infinite number of waveguides is considered. Computer simulations are provided together with the proven experimental results. It is shown that there is a threshold of channel separation due to channel cross-coupling, which results in a tradeoff between channel packing density and interconnect distance. Waveguide dimension closer to the cutoff boundary of second mode (E₁₂ ^x) is preferred for an optimum design     

Polymer Optical Interconnects—A Scalable Large-Area Panel Processing Approach

A flexible approach to producing optical interconnects on 609.6$ast ,$609.6 mm large-area panels is demonstrated. Stepwise projection patterning from 101.6$ast ,$101.6 mm masks has generated optical waveguide patterns over the whole panel using large-area projection lithography equipment. The waveguide routing design allows optical waveguides on different 101.6$ast ,$101.6 mm tiles to be interconnected. Four different waveguide connecting geometries in the border region between tiles have been fabricated and tested. Multimode waveguides from inorganic-organic hybrid polymers (ORMOCER) (cross section:$le hbox 50~muhbox mast hbox 10~muhbox m$) with refractive index step between core and cladding$Delta n=hbox 0.01$were produced. The index step was adjusted by mixing two diffrent ORMOCER systems. The materials show good adhesion to numerous substrates, such as glass and silicon. Application concepts such as flexible manufacturing of optoelectrical hybrid backplanes with two-dimensional interconnect, a three-dimensional optical interconnect with optical vias, and a hybrid backplane with the optical interconnect in a strip-format on a separate plane right above the electrical plane are proposed. Promising new technologies are presented along with preliminary demonstrativ viability.     

Full-Wave Analysis of Large-Scale Interconnects Using the Multilevel UV Method With the Sparse Matrix Iterative Approach (SMIA)

Moving towards the goal of analyzing whole printed circuit boards (PCBs) and packages using full-wave electromagnetic (EM) methods, the multilevel UV method is applied to the method-of-moments (MoM) solution of the current on large-scale interconnects. The MoM solution uses the layered media Green's functions computed using the numerical modified steepest-descent path (NMSP) method, and is applied to the exterior layers of the interconnect structure. The sparse matrix iterative approach (SMIA) is used to speed up the solution of the iterative matrix solver. The iterative solver is also accelerated by using larger blocks in the block diagonal inverse preconditioner. With the multilevel UV method, a fast solution is presented for solving the current on large-scale interconnects on thin layered structures at high frequencies. We show an example of an interconnect structure that has horizontal dimensions of 12.675 $lambda$ $times$ 12.876 $lambda$ with 24$thinspace$ 848 current unknowns and an interconnect fractional area of approximately 31%. This problem takes a total of 21 min 20 s to solve for the current on the traces on a Pentium 3.2-GHz CPU with 4 GB of RAM.      

Design limitations of highly parallel free-space opticalinterconnects based on arrays of vertical cavity surface-emitting laserdiodes, microlenses, and photodetectors

We utilize a novel diffraction formalism to study the crosstalk effect in a highly parallel free-space optical interconnect based on two-dimensional arrays of surface-emitting laser diodes, microlenses, and photodetectors. The diffraction induced crosstalk between adjacent laser diodes in each detector to the system limitations is investigated. Optimum design rules and formulas are given for the first time, to include the relation of channel packaging density and interconnect length to the design parameters of the optical interconnect components. The design formulas developed here yield an optimum detector size and indicate a tradeoff between channel packaging density and interconnect length. The feasibility of such a free-space interconnect with a channel packaging density of 3460 channels/cm² and 2.0 cm interconnection length is determined using typical parameters of detector radius from ~5 to ~45 μm, lens radius of 85 μm, and laser diode radius of ~5 pm operating at wavelength 0.67 pm for signal-to-noise ratio above 17 dB. Some experiments were conducted to measure the diffraction induced crosstalk and optical link efficiency     

Optical Data Link Employing Organic Light-Emitting Diodes and Organic Photodiodes as Optoelectronic Components

An optical interconnect solely using organic optoelectronic components is presented. The data link is based on an organic light-emitting diode as the transmitter and an organic photodiode as the receiver. Light is transmitted via a polymer optical fiber coupled to the active components. A digitized audio signal based on the Sony/Philips Digital Interface Format standard at a signal bit rate of 2.8224 Mbit/s (44.1-kHz sampling frequency) is successfully transmitted.     

In Situ Interferometric Monitoring of Fiber Insertion in Fiber Connector Components

We present an interferometric setup for in situ monitoring of fiber tip positions when inserting optical fibers for fixation in fiber connector components. It ensures an accurate fiber tip position at the fiber connector's front facet and across the fiber array in cases where postinsertion polishing is not possible. We demonstrate our technique by populating a plastic fiber connector for optical interconnect applications, and compare the fiber tip position measured in situ using our setup with the position measured off-line using a commercial white light interferometer, showing a deviation smaller than 5%.      

Multistability in Bistable Ferroelectric Materials toward Adaptive Applications

Traditionally thermodynamically bistable ferroic materials are used for nonvolatile operations based on logic gates (e.g., in the form of field effect transistors). But, this inherent bistability in these class of materials limits their applicability for adaptive operations. Emulating biological synapses in real materials necessitates gradual tuning of resistance in a nonvolatile manner. Even though in recent years few observations have been made of adaptive devices using a ferroelectric, the principal question as to how to make a ferroelectric adaptive has remained elusive in the literature. Here, it is shown that by locally controlling the nucleation energy distribution at the ferroelectric–electrode interface multiple‐addressable states in a ferroelectric can be created, which is necessary for adaptive/synaptic applications. This is realized by depositing a layer of nonswitchable ZnO on top of thin film ferroelectric PbZr _x Ti_{(1– x )}O₃. This methodology of interface‐engineered ferroelectric should enable realising brain‐like adaptive/synaptic memory in complementary metal‐oxide‐semiconductor (CMOS) devices. Furthermore, the temporally stable multistability in ferroelectrics should enable the designing of multistate memory and logic devices.     

Selfrouting optical interconnects

A new type of selfrouting optical interconnect (SROI) is described where an optical signal beam or optical data packet is routed to a destination using an all optical switch where the destination is defined within the optical signal by the autocorrelation function of the optical signal.<>     

Low-temperature capacitor-over-interconnect (COI) Modular FeRAM for SOC application

A complete capacitor-over-interconnect (COI) modular ferroelectric random access memory (FeRAM) is demonstrated. A zero switching time transient approach is adopted to extract the HSPICE model files, and a 128-Kb 1T/1C/ 64-Kb 2T/2C dual function test chip is designed. A novel plate line-driven while bit line (BL)-driven operation scheme is used to achieve fast access speed. In order to build the capacitor-over-interconnect (COI) structure, the FeRAM capacitor must be built at <450/spl deg/C. By using a conductive perovskite LaNiO/sub 3/ (LNO) bottom electrode as seed layer, the crystallization temperature of in situ sputter deposited PZT is greatly reduced to 400/spl deg/C/spl sim/450/spl deg/C. This low processing temperature allows the stacking of ferroelectric capacitor on top of CMOS interconnect. The 2Pr value of the low-temperature grown PZT is about 20 /spl mu/C/cm/sup 2/ and provides 130-400 mV of sensing margin even with high BL capacitance of 800 fF.     

A photonic knockout switch for high-speed packet networks

A high-performance packet switch is discussed which uses a photonic interconnect fabric to route very-wideband data packets from input to output. Packet contention is accomplished using a much slower electronic controller, based on the knockout principle operating in parallel with the optical interconnect. Specifically, the use of a wavelength-division-multiplex fabric whereby high-speed (2-4 Gb/s) packets are regenerated before modulating a single-frequency laser at each switch input. The optical signals from various inputs are summed in a star coupler and then broadcast to the different coupler outputs. Each coupler is equipped with a small number (L) of tunable receivers arranged in a parallel manner, each preceded by a power splitter so that up to L simultaneous packets can be received by each output. The L packets so received are stored in an L-input one-output first-in first-out (FIFO) buffer so that the FIFO packet sequence is always guaranteed. Not only does this architecture achieve the best delay-throughput performance, but, remarkably, modularity is such that the optical complexity grows linearly with the number of switch ports./     

High-speed wavelength-division multiplexing and demultiplexingusing monolithic quasi-planar VCSEL and resonant photodetector arrayswith strained InGaAs quantum wells

We demonstrate the high-speed (gigabit-per-second) operation of a wavelength-division-multiplexed optical interconnect, which is implemented by multiplexing the optical data from a multiple-wavelength vertical-cavity surface-emitting laser (VCSEL) array into a single optical fiber, and demultiplexing the composite data stream using an array of resonance-enhanced photodetectors (REPDs) with matching resonance wavelengths. By using VCSELs and REPDs with a new quasi-planar oxide-confinement design for improved high-speed performance, and using strained InGaAs-GaAs quantum wells to achieve a better tradeoff between optical responsivity and wavelength selectivity, wavelength-division-multiplexing (WDM) operation has been demonstrated under 1-Gb/s data modulation, with an optical crosstalk rejection ratio of better than -10 dB for wavelength channels that are spaced 4 nm apart     

Synchronous Parallel Optical I/O on CMOS: A Case Study of the Uniformity Issue

Short-range parallel optical interconnect between integrated circuits can alleviate bandwidth, power, and packaging density issues that are associated with low-latency high-bandwidth input-output over electrical interconnect. In this paper, we evaluate the option of using true source-synchronous signaling over optical interconnect with a large number of channels, reducing the substantial per-channel clock synchronization circuitry to one instance. We also look into dc-unbalanced signaling to remove the need for data coding. Uniformity across channels is key to the feasibility of such an approach. An actual 64-channel parallel optical interconnect setup at 1.25 Gb/s/channel is examined, and models for the performance and uniformity of the different constituent parts of the interconnect are drawn up. Major attention is given to the statistical modeling of the coupling efficiency between a vertical cavity surface emitting laser array and a multifiber connector. Although derived in the context of a uniformity study, the stochastic models and the modeling approach are valuable in their own right. In our case study, the usage of a common logic threshold across all channels, which is required for dc-unbalanced signaling, appears infeasible after all models are combined. Efficient true source-synchronous signaling turns out to be within reach in carefully designed systems.     

Two-Dimensional Ferroelectric Photonic Crystal Waveguides: Simulation, Fabrication, and Optical Characterization

The optical properties of two dimensional photonic crystal (PhC) waveguides were investigated using ferroelectric barium titanate (BTO) thin films as the optical medium. The photonic band structure was calculated using a 2-D finite difference time domain (FDTD) method; a broad band gap is observed that results from the high refractive index contrast. The simulated transmission spectra indicate the stop band of PhC is mainly determined by three parameters: lattice constant, refractive index contrast, and waveguide mode order. From transmission measurements the PhC with a lattice constant ${a}=420$ nm shows a strong light dispersion and the other PhC with ${a}=450$ nm shows a 120-nm broad stop band. Strong localization of visible light within the PhC cavities is demonstrated from the light scattering images. The observed strong light confinement and its spatial intensity profile due to resonance agree with the calculated profiles. From polarized optical microscopy we discovered the scattered light wavelength was highly sensitive to magnitude of the lattice constant. The optical scattering properties indicate BTO PhC can potentially serve as micrometer size electro-optically tunable switches and color filters.      

Optical I/O Technology for Tera-Scale Computing

This paper describes both a near term and a long term optical interconnect solution, the first based on a packaging architecture and the second based on a monolithic photonic CMOS architecture. The packaging-based optical I/O architecture implemented with 90 nm CMOS transceiver circuits, 1 × 12 VCSEL/detector arrays and polymer waveguides achieves 10 Gb/s/channel at 11 pJ/b. A simple TX pre-emphasis technique enables a potential 18 Gb/s at 9.6 pJ/b link efficiency. Analysis predicts this architecture to reach less than 1 pJ/b at the 16 nm CMOS technology node. A photonic CMOS process enables higher bandwidth and lower energy-per-bit for chip-to-chip optical I/O through integration of electro-optical polymer based modulators, silicon nitride waveguides and polycrystalline germanium (Ge) detectors into a CMOS logic process. Experimental results for the photonic CMOS ring resonator modulators and Ge detectors demonstrate performance above 20 Gb/s and analysis predicts that photonic CMOS will eventually enable energy efficiency better than 0.3 pJ/b with 16 nm CMOS. Optical interconnect technologies such as these using multi-lane communication or wavelength division multiplexing have the potential to achieve TB/s interconnect and enable platforms suitable for the tera-scale computing era.     

An 8-Gb/s optical backplane bus based on microchannelinterconnects: design, fabrication, and performance measurements

We describe the characteristics of a microchannel-based optical backplane including signal-to-noise ratio (SNR), interconnect distances, and data transfer rates. The backplane employs 250 μm-spacing two-dimensional (2-D) vertical cavity surface emitting lasers (VCSELs) and a microlens array to implement 500 μm-, 750 μm-, and 1-mm optical beam arrays. By integrating the transmitter and a multiplexed polymeric hologram as a deflector/beam-splitter for the guided-wave optical backplane, the result demonstrates a multibus line architecture and its high-speed characteristics. Maximum interconnect distances of 6 cm and 14 cm can be achieved to satisfy 10^-12 bit error rate (BER) using 2×2 beams of 500 μm- and 1 mm-spacing array devices. The total data transfer rate of the developed backplane has shown 8 Gb/s from eye diagram measurements