Si/CdTe复合衬底HgCdTe液相外延材料的生长与性能分析

通过改进推舟液相外延技术,成功地在(211)晶向Si/CdTe复合衬底上进行了HgCdTe液相外延生长,获得了表面光亮的HgCdTe外延薄膜.测试结果表明,(211)Si/CdTe复合衬底液相外延HgCdTe材料组分及厚度的均匀性与常规(111)CdZnTe衬底HgCdTe外延材料相当;位错腐蚀坑平均密度为(5～8)×105 cm-2,比相同衬底上分子束外延材料的平均位错密度要低一个数量级;晶体的双晶半峰宽达到70″左右.研究结果表明,在发展需要低位错密度的大面积长波HgCdTe外延材料制备技术方面,Si/CdTe复合衬底HgCdTe液相外延技术可发挥重要的作用.     

Si/CdTe复合衬底HgCdTe液相外延材料的生长与性能分析

通过改进推舟液相外延技术,成功地在(211)晶向Si/CdTe复合衬底上进行了HgCdTe液相外延生长,获得了表面光亮的HgCdTe外延薄膜.测试结果表明,(211)Si/CdTe复合衬底液相外延HgCdTe材料组分及厚度的均匀性与常规(111)CdZnTe衬底HgCdTe外延材料相当;位错腐蚀坑平均密度为(5～8)×105 cm-2,比相同衬底上分子束外延材料的平均位错密度要低一个数量级;晶体的双晶半峰宽达到70″左右.研究结果表明,在发展需要低位错密度的大面积长波HgCdTe外延材料制备技术方面,Si/CdTe复合衬底HgCdTe液相外延技术可发挥重要的作用.     

偏转角(211)Si基CdTe复合衬底研究

晶面偏角是提高(211) Si基CdTe复合衬底质量的方法之一。通过对偏转角Si基CdTe复合衬底分子束外延工艺的研究,发现2°和3°偏转角(211)Si基CdTe复合衬底在晶体质量方面优于标准(211)Si基CdTe复合衬底,是未来提高Si基CdTe复合衬底质量的新方向。     

基于正交设计的Si基复合衬底优化工艺试验

在正交设计的基础上,通过一系列工艺测试实验,研究了MEE外延温度、MEE退火温度、CdTe外延温度、CdTe退火温度对Si基复合衬底的两个关键质量因素FWHM和表面粗糙度的影响。通过统计技术对测得的实验数据进行了方差分析,结果表明,CdTe退火温度是影响FWHM的关键因子,MEE退火温度和CdTe外延温度对Ra值来说影响是显著的。通过该系列实验得到最优的外延工艺条件。     

硅缓冲层提高选区外延生长硅基锗薄膜质量

研究了Si缓冲层对选区外延Si基Ge薄膜的晶体质量的影响。利用超高真空化学气相沉积系统,结合低温Ge缓冲层和选区外延技术,通过插入Si缓冲层,在Si/SiO_2图形衬底上选择性外延生长Ge薄膜。采用X射线衍射(XRD)、扫描电子显微镜(SEM)、原子力显微镜(AFM)表征了Ge薄膜的晶体质量和表面形貌。测试结果表明,选区外延Ge薄膜的晶体质量比无图形衬底外延得到薄膜的晶体质量要高;选区外延Ge薄膜前插入Si缓冲层得到Ge薄膜具有较低的XRD曲线半高宽以及表面粗糙度,位错密度低至5.9×10~5/cm^2,且薄膜经过高低温循环退火后,XRD曲线半高宽和位错密度进一步降低。通过插入Si缓冲层可提高选区外延Si基Ge薄膜的晶体质量,该技术有望应用于Si基光电集成。     

Si基大面积碲镉汞分子束外延研究

文章报道了Si基碲镉汞分子束外延(MBE)的最新研究进展。尝试用晶向偏角降低高界面应变能的方法,摸索大失配体系中位错的抑制途径,寻找位错密度与双晶半峰宽的对应关系,基本建立了外延材料晶体质量无损检测评价标准,并对外延工艺进行指导。通过上述研究,15~20μm Si基CdTe复合材料双晶半峰宽最好结果为54arcsec,对应位错密度(EPD)小于2×106/cm2,与相同厚度的GaAs/CdTe(211)双晶水平相当,达到或优于国际最好结果。获得的3 in 10μm Si基HgCdTe材料双晶半峰宽最好结果为51arcsec,目前Si基HgCdTe材料已经初步应用于焦平面中波320×240器件制备。     

Si基CdTe复合衬底分子束外延研究

文章引入晶格过渡的Si/ZnTe /CdTe作为复合外延基底材料,以阻挡Si/HgCdTe之间大晶格失配产生的高密度位错。通过对低温表面清洁化、面极性控制和孪晶抑制等的研究,解决了Si基CdTe分子束外延生长中诸多的技术难题。在国内首次采用分子束外延(MBE)的方法获得了大面积的Si基CdTe复合衬底材料,对应厚度为4～4. 4μm Si/CdTe (211)样品双晶半峰宽的统计平均结果为83弧秒,与相同厚度的GaAs/CdTe (211)双晶平均水平相当。     

Si基CdTe/HgCdTe分子束外延材料的位错抑制

基于GaAs/Si材料中位错的运动反应理论,修正获得CdTe/Si和HgCdTe/Si外延材料中的位错运动反应模型.采用快速退火方法对Si基HgCdTe外延材料进行位错抑制实验研究,实验结果与理论曲线基本吻合,从理论角度解释了不同高温热处理条件对材料体内位错的抑制作用.对于厚度为4～10μnn的CdTe/Si进行500...     

Si衬底GaN基多量子阱外延材料的TEM研究

本文采用高分辨透射电子显微技术对在Si衬底生长的GaN基多量子阱外延材料的位错特征、外延层与衬底的晶体取向关系及界面的结晶形态等微观结构进行了分析和研究.结果表明:Si衬底生长的GaN与衬底有一定的取向关系;材料在MQW附近的穿透位错密度达108 cm-2量级,且多数为刃型位错;样品A的多量子阱下方可见平行于界面方向的...     

分子束外延CdTe（211）B／Si复合衬底材料

报道了用MBE的方法，在3英寸Si衬底上制备ZnTe／CdTe（211）B复合衬底材料的初步研究结果，该研究结果将能够直接应用于大面积Si基HgCdTe IRFPA材料的生长．经过Si（211）衬底低温表面处理、ZnTe低温成核、高温退火、高温ZnTe、CdTe层的生长研究，用MBE方法成功地获得了3英寸Si基ZnTe／CdTe（211）B复合衬底材料．CdTe厚度大于10μm，XRD FWHM平均值为120arc sec，最好达到100arc sec，无（133）孪晶和其他多晶晶向．     

Feasibility of Localized Substrate Thinning for Reduced Dislocation Density in CdTe/Si Heterostructures

HgCdTe heteroepitaxy on low-cost, large-lattice-mismatched substrates such as Si continue to be plagued by large threading dislocation densities that ultimately reduce the operability of the thermal imaging detector array. Molecular-beam epitaxy (MBE) of 10 μm- to 15 μm-thick CdTe buffer layers has played a crucial role in reducing dislocation densities to current state-of-the-art levels. Herein, we examine the possibility that growth on locally back-thinned substrates could prove advantageous in further reducing dislocation densities in the CdTe/Si heteroepitaxial system. Using defect decoration techniques, a decrease in dislocation (etch-pit) density of up to ~42% has been measured in CdTe regions where the underlying Si substrate was chemically back-thinned to ~20 μm. A theoretical understanding is proposed, where a substrate-thickness-dependent dislocation image force is a likely cause for the experimentally observed reduction in threading dislocation density. These observations raise the prospect of combining localized substrate thinning with other techniques to further reduce dislocation densities to levels sought for HgCdTe/CdTe/Si and other large-lattice-mismatched systems.     

Recent Progress in MBE Growth of CdTe and HgCdTe on (211)B GaAs Substrates

Alternate substrates for molecular beam epitaxy growth of HgCdTe including Si, Ge, and GaAs have been under development for more than a decade. MBE growth of HgCdTe on GaAs substrates was pioneered by Teledyne Imaging Sensors (TIS) in the 1980s. However, recent improvements in the layer crystal quality including improvements in both the CdTe buffer layer and the HgCdTe layer growth have resulted in GaAs emerging as a strong candidate for replacement of bulk CdZnTe substrates for certain infrared imaging applications. In this paper the current state of the art in CdTe and HgCdTe MBE growth on (211)B GaAs and (211) Si at TIS is reviewed. Recent improvements in the CdTe buffer layer quality (double crystal rocking curve full-width at half-maximum?≈?30?arcsec) with HgCdTe dislocation densities of ≤10⁶?cm^?2 are discussed and comparisons are made with historical HgCdTe on bulk CdZnTe and alternate substrate data at TIS. Material properties including the HgCdTe majority carrier mobility and dislocation density are presented as a function of the CdTe buffer layer quality.     

Te-rich liquid phase epitaxial growth of HgCdTe on Si-based substrates

The growth of high quality (111)B oriented HgCdTe layers on CdZnTe/GaAs/Si and CdTe/Si substrates by Te-rich slider liquid phase epitaxy (LPE) is reported. Although the (111) orientation is susceptible to twinning, a reproducible process yielding twin-free layers with excellent surface morphology has been developed. The electrical properties and dislocation density in films grown on these substrates are comparable to those measured in HgCdTe layers grown on bulk CdTe substrates using the same LPE process. This is surprising in view of the large lattice mismatch that exists in these systems. We will report details of both the substrate and HgCdTe growth processes that are important to obtaining these results.     

Growth and Analysis of HgCdTe on Alternate Substrates

Dislocations generated at the HgCdTe/CdTe(buffer layer) interface are demonstrated to play a significant role in influencing the crystalline characteristics of HgCdTe epilayers on alternate substrates (AS). A dislocation density >10⁸?cm^?2 is observed at the HgCdTe/CdTe interface. Networks of dislocations are generated at the HgCdTe/CdTe interface. The dislocation networks are observed to entangle. Significant dislocation reduction occurs within a few microns of the HgCdTe/CdTe interface. The reduction in dislocation density as a function of depth is enhanced by annealing. Etch pit density and x-ray diffraction full-width at half-maximum values increase as a function of the lattice mismatch between HgCdTe epilayer and the buffer layer/substrate. The experimental results suggest that only by reducing HgCdTe/CdTe lattice mismatch will the desired crystallinity be achieved for HgCdTe epilayers on AS.     

多层HgCdTe异质外延材料的热退火应力分析

前期研究采用高温热处理方法,获得了抑制位错的最佳退火条件.通过比对实验,发现不同衬底上HgCdTe表面的CdTe钝化层在热处理过程中对位错的抑制作用各有不同.结合晶格失配应力和热应力对不同异质结构进行理论计算,借助X射线摇摆曲线的倒易空间分析,解释了CdTe钝化层对HgCdTe位错抑制的影响作用.     

Selective CdTe Nanoheteroepitaxial Growth on Si(100) Substrates Using the Close-Spaced Sublimation Technique Without the Use of a Mask

The development of HgCdTe detectors requires high sensitivity, small pixel size, low defect density, long-term thermal-cycling reliability, and large-area substrates. CdTe bulk substrates were initially used for epitaxial growth of HgCdTe films. However, CdTe has a lattice mismatch with long-wavelength infrared (LWIR) and middle-wavelength infrared (MWIR) HgCdTe that results in detrimental dislocation densities above mid-10⁶ cm^?2. This work explores the use of CdTe/Si as a possible substrate for HgCdTe detectors. Although there is a 19% lattice mismatch between CdTe and Si, the nanoheteroepitaxy (NHE) technique makes it possible to grow CdTe on Si substrates with fewer defects at the CdTe/Si interface. In this work, Si(100) was patterned using photolithography and dry etching to create 500-nm to 1-μm pillars. CdTe was selectively deposited on the pillar surfaces using the close-spaced sublimation (CSS) technique. Scanning electron microscopy (SEM) was used to characterize the CdTe selective growth and grain morphology, and transmission electron microscopy (TEM) was used to analyze the structure and quality of the grains. CdTe selectivity was achieved for most of the substrate and source temperatures used in this study. The ability to selectively deposit CdTe on patterned Si(100) substrates without the use of a mask or seed layer has not been observed before using the CSS technique. The results from this study confirm that CSS has the potential to be an effective and low-cost technique for selective nanoheteroepitaxial growth of CdTe films on Si(100) substrates for infrared detector applications.     

Impurity Gettering in (112)B HgCdTe/CdTe/Alternate Substrates

The crystalline structure and impurity profiles of HgCdTe/CdTe/alternate substrate (AS; Si and GaAs are possibilities) and CdTe/AS were analyzed by secondary-ion mass spectrometry, atomic force microscopy, etch pit density analysis, and scanning transmission electron microscopy. Impurities (Li, Na, and K) were shown to getter in as-grown CdTe/Si epilayers at in situ Te-stabilized thermal anneal (~500°C) interfaces. In HgCdTe/CdTe/Si epilayers, indium accumulation was observed at Te-stabilized thermal anneal interfaces. Impurity accumulation was measured at HgCdTe/CdTe and CdTe/ZnTe interfaces. Processing anneals were found to nearly eliminate the gettering effect at the in situ Te-stabilized thermal anneal interfaces. Impurities were found to redistribute to the front HgCdTe/CdTe/Si surface and p–n junction interfaces during annealing steps. We also investigated altering the in situ Te-stabilized thermal anneal process to enhance the gettering effect.     

Long wavelength infrared, molecular beam epitaxy, HgCdTe-on-Si diode performance

In the past several years, we have made significant progress in the growth of CdTe buffer layers on Si wafers using molecular beam epitaxy (MBE) as well as the growth of HgCdTe onto this substrate as an alternative to the growth of HgCdTe on bulk CdZnTe wafers. These developments have focused primarily on mid-wavelength infrared (MWIR) HgCdTe and have led to successful demonstrations of high-performance 1024×1024 focal plane arrays (FPAs) using Rockwell Scientific’s double-layer planar heterostructure (DLPH) architecture. We are currently attempting to extend the HgCdTe-on-Si technology to the long wavelength infrared (LWIR) and very long wavelength infrared (VLWIR) regimes. This is made difficult because the large lattice-parameter mismatch between Si and CdTe/HgCdTe results in a high density of threading dislocations (typically, >5E6 cm⁻²), and these dislocations act as conductive pathways for tunneling currents that reduce the R_oA and increase the dark current of the diodes. To assess the current state of the LWIR art, we fabricated a set of test diodes from LWIR HgCdTe grown on Si. Silicon wafers with either CdTe or CdSeTe buffer layers were used. Test results at both 78 K and 40 K are presented and discussed in terms of threading dislocation density. Diode characteristics are compared with LWIR HgCdTe grown on bulk CdZnTe.     

异质衬底外延碲镉汞薄膜位错抑制技术进展

分子束外延碲镉汞技术是制备第三代红外焦平面探测器的重要手段,基于异质衬底的碲镉汞材料具有尺寸大、成本低、与常规半导体设备兼容等优点,是目前低成本高性能红外探测器发展中的研究重点。对异质衬底上碲镉汞薄膜位错密度随厚度的变化规律进行了建模计算,结果显示ρ~1/h模型与实验结果吻合度好,异质衬底上原生碲镉汞薄膜受位错反应半径制约,其位错密度无法降低至5×10 6 cm-2以下,难以满足长波、甚长波器件的应用需求。为了有效降低异质外延的碲镉汞材料位错密度,近年来出现了循环退火、位错阻挡和台面位错吸除等位错抑制技术,本文介绍了各技术的原理及进展,分析了后续发展趋势及重点。循环退火和位错阻挡技术突破难度大,发展潜力小,难以将碲镉汞位错密度控制在5×105 cm-2以内。台面位错吸除技术目前已经显示出了巨大的发展潜力和价值,后续与芯片工艺融合后,有望大幅促进低成本长波、中长波、甚长波器件的发展。