硅外延层中的杂质

主掺杂质、固态外扩散杂质、气相自掺杂质、系统自掺杂质和金属杂质等五类杂质源是外延层中的常见杂质。主掺杂质决定外延层的电阻率。固态外扩散、气相自掺杂和系统自掺杂影响衬底界面附近的外延层杂质浓度的深度分布。金属杂质在外延层中对器件有害。本文系统地介绍了掺杂源的掺杂过程也给出了控制的方法。     

重掺磷衬底上外延层生长工艺研究

重掺磷衬底上硅外延片是制作集成电路开关电源的肖特基二极管和场控高频电力电子器件的首选产品。重掺磷衬底外延片可以大幅降低压降中半导体部分引起的压降所占的比例。介绍了重掺磷外延片的一种实用生产技术,在高浓度衬底外延后失配现象、杂质外扩抑制方法、减少外延过程中衬底磷杂质的挥发等方面进行了研究。在研究的基础上使用CSD公司的EpiPro5000型外延设备进行工艺试验,采用盖帽层分层生长、变流量赶气和低温度生长等工艺条件控制磷杂质的扩散和挥发,从而减少自掺杂效应,获得良好的电阻率均匀性和陡峭的外延层过渡区。试验结果已成功应用于大规模生产,得到了用户认可。     

p型硅外延层电阻率的控制

计算表明，ｐ型硅外延层的电阻率对其生长速度和生长温度的变化都是十分敏感的。为了保证ｐ型硅外延片的电阻率具有良好的可控性和重现性，除了充分抑制重掺硼衬底的自掺杂作用外，还需十分严格地控制硅外延片的生长温度和速度。     

高阻薄层硅外延材料研制

根据绝大多数分立器件的技术要求,常规硅外延层电阻率的数值会小于厚度的数值。介绍了一种外延层电阻率数值接近甚至大于厚度数值的高阻薄层硅外延材料的实用生产技术,即在PE-2061S桶式外延设备上,采取特殊的工艺方法,在掺砷(As)衬底上进行高阻薄层外延生长。该工艺通过控制自掺杂,改善了纵向载流子浓度分布,取得了较好的外延参数均匀性。     

200 mm Trench MOSFET管用硅外延电阻率管控

200 mm重掺As衬底的MOSFET外延片在后续芯片制程中,由于还需要经历高温环节(大于1100℃),因此衬底中As的自掺杂效应将再次出现,从而使外延片边缘区域的电阻率降低明显。在外延过程中,需要将外延片边缘区域的电阻率有意控制略高于中心区域。在控制过程中通过引入Offset(差值)的管理方法,确保外延层边缘3 mm区域与中心区域的偏差减小,从而实现片内管芯之间性能一致。     

失效器件分析

As重掺杂Si片的电阻率可低到10-3 Ω·cm,可用作外延片的衬底材料,对于正向压降低的半导体器件来说,用这类外延片制作器件是最恰当的选择.As重掺杂Sj片在外延时容易产生气相自掺杂,尤其是同型外延时还存在固态外扩散现象,在整个制作器件过程中易产生工艺参数偏差,导致器件性能下降,严重时器件失效,当然衬底材料也可以选用价格较高的背处理工艺Si片,能有效地抑制由于后续加工工艺产生的许多缺陷.对某生产厂生产的一批器件电参数性能下降的原因进行了剖析,分析阐明了以As重掺杂Si片为衬底的外延片中衬底杂质对器件质量的影响.     

平板式外延炉大尺寸硅外延层的均匀性调控

硅外延层是在硅单晶抛光衬底上采用化学气相沉积方法生长的一层单晶硅薄膜。本实验以150 mm的大尺寸硅抛光片为衬底生长高均匀性外延层，结合傅里叶变换红外线光谱分析（FT-IR）、电阻率测试仪等测试设备对外延层电学参数进行了分析。对平板式外延炉的流场、热场与厚度、电阻率均匀性的相互作用规律进行了研究，最终制备出表面质量良好、片内和片间不均匀性小于1%的外延层。     

衬底去边宽度对高阻厚层硅外延片参数的影响

硅外延片的参数受衬底以及外延层两方面影响,研究了衬底背面SiO2层边缘去除宽度(简称去边宽度)对高阻厚层硅外延片参数的影响.对比0、0.3和0.5 mm三种去边宽度硅外延片的参数发现,去边宽度对外延层厚度不均匀性没有影响,对外延层电阻率不均匀性影响巨大,外延层电阻率不均匀性与衬底去边宽度呈正比.衬底去边宽度也会影响外延片的外观、表面颗粒以及滑移线.进一步研究了去边宽度对后续制备MOS管在晶圆片内击穿电压分布的影响,发现去边宽度越宽,晶圆片内MOS管击穿电压差越大.综合考虑外延片及其制备器件参数,选择0.3 mm为制备高阻厚层硅外延片的最佳去边宽度,可以获得优良的外延片参数及器件特性.     

重掺砷衬底外延工艺研究

在重掺砷（As）衬底上生长外延层一直是外延工艺难点。外延工艺过程中由于衬底的掺杂浓度与外延层的掺杂浓度相差很大,自掺杂与固态外扩散现象严重,使得外延过渡区变宽,工艺很难控制。在确保外延层晶格结构完整、表面质量完美的前提下,适当增加外延生长速率、降低外延生长温度可减小自掺杂与固态外扩散的影响。结合多晶硅背封法、二步外延法等对工艺过程进行优化,可有效抑制自掺杂现象从而提高外延片的质量。     

功率VDMOS器件用硅外延材料研制

文章阐述了硅功率VDMOS器件的基本原理和器件结构,也展现了作为电力电子器件其广阔的应用领域,提出了功率VDMOS器件对硅外延材料的要求和发展方向。依据功率器件对外延片的要求,通过优化外延工艺程序和优化外延工艺参数,消除或减弱了自掺杂对电阻率均匀性的影响,消除了过渡区对厚度均匀性的影响,也较好地控制了外延层中的结构缺陷...     

Growth of n-Si layers by molecular-beam epitaxy on the substrates heavily doped with boron

Epitaxial n-Si layers doped with phosphorus or erbium have been grown by sublimation molecularbeam epitaxy at 500°C on heavily boron-doped p ⁺-type substrates with resistivity ρ = 0.005 Ω cm. Distribution profiles of the B, Er, and O impurity concentrations in the samples were determined by secondary-ion mass spectrometry. A thermal annealing of the substrate in vacuum at 1300°C for 10 min and growth at a very low substrate temperature made it possible to obtain an extremely abrupt profile for doping impurities at the layer-substrate interface. This method for growth of n-p ⁺ junctions considerably improves their electrical and luminescent characteristics.     

Methods for the doping of silicon layers in growth by sublimation MBE

Epitaxial layers doped with various impurities were grown by sublimation MBE on Si (100) substrates. Doping with phosphorus was controlled at electron densities ranging from 2×10¹³ to 10¹⁹ cm^?3. A high dopant concentration of ～10²⁰ cm^?3 was obtained from the evaporation of partly molten Si sources. It shown that the type and concentration of an impurity in the sublimation MBE process can be controlled by the fabrication of multilayer p ⁺?n ⁺ structures.     

p型单晶硅涂源掺锰新方法

研究了扩散源的浓度与掺杂后硅材料补偿度之间的关系。以MnCl2·4H2O乙醇溶液为扩散源,涂在初始电阻率为3.8?·cm的p型单晶硅片表面,在高温(1200℃)下掺杂锰后,在室温避光条件下,用SDY—5型双电测四探针仪测样品电阻率ρ。改变扩散源的浓度重复实验,用XRD对扩散后的样品进行分析,结果表明:当硅片表面浓度为23.4×10–8mol/cm2时,扩散后样品体电阻率的径向不均匀度在5%以内,扩散后硅片的补偿度最大。     

瞬态电压抑制器的减压外延工艺研究

瞬态电压抑制器是用于保护高频电路电压瞬变和浪涌防护的半导体器件,由低击穿电压的雪崩二极管和低电容二极管组成。低电容二极管需要在高掺杂的P型衬底上生长近似本征的超高电阻率的N型外延层。该工艺面临的难点在于如何减少P型自掺杂并稳定控制外延层的电阻率。文章利用扩展电阻测试方法重点研究了8英寸化学气相外延减压工艺中工艺参数对外延层质量的影响和对图形畸变的影响。     

A model of reduction of oxidation-enhanced diffusion in heavily doped Si layers

A model of reduction of oxidation-enhanced diffusion (OED) in heavily doped Si layers via bulk recombination of self-interstitials at centers associated with the dopant is suggested. The allowance made for the recombination of excess self-interstitials, which are generated upon thermal oxidation, allows one to describe the dependence of OED reduction on the doping level. The experimental data on the OED of B and P impurities in uniformly doped Si layers are analyzed. From the analysis, the recombination-rate constants are determined and capture radii are estimated for various variants of interaction of excess self-interstitials with impurity atoms and impurity-vacancy pairs.     

Doping of trench capacitors by rapid thermal diffusion

A new rapid thermal diffusion process for shallow, heavily doped trench junctions in high density dynamic RAMs is described. Planar dopant sources are formed by spin-coating rigid substrates, such as silicon wafers or solid dopant sources, with liquid dopants. Diffusion takes place at high temperatures when the source, placed in proximity to the silicon wafer, releases dopant via evaporation followed by diffusion to the silicon surface. Well-controlled, heavily doped shallow junctions are readily obtained for B, P, and As. The doping process is shown to provide uniform doping of high-aspect-ratio trenches. Process control is achieved by controlling the wafer temperature and duration of the process. Junction depths near 0.1 μm have been demonstrated over the entire surface of trenches 0.7 μm in diameter and 6 μm in depth     

Silicon doping by nuclear transmutation

This paper describes, from the view of nuclear physics and radiochemistry, the mode of operation in doping semiconductor silicon with phosphorus by neutron irradiation. In addition to precise control of the irradiation fluence, this includes control of neutron-flux distribution, self-shielding and radioactive products from the silicon matrix and the surface impurities. The accuracy of the resistivity values achieved by this method is better than ± 5% at the predicated value. The good homogeneity of the dopant distribution is shown by the results of location-resolving resistivity measurements as well as by the breakdown radiation emitted by diodes. Neutron-bombarded homogeneously doped silicon (NBH-silicon) is used for routine manufacture of multi-diode vidicons and power devices.     

Resistivity and deep impurity levels in silicon at 300 K

Families of curves of the resistivity at 300 K for n- and p-type silicon doped with deep activation energy impurities are presented as a function of impurity concentration. These curves are based on analyses of Irvin's curves, applicable to the shallow activation energy impurities, and on the properties of the deeper activation energy impurities. These curves apply to impurities with activation energies that are independent of concentration. Since Irvin's p-type curve appears to be heavily influenced by Si:Ga data in the 10¹⁶-10¹⁸-cm^-3range, a boron curve is calculated for this range. This curve may be considered a correction to Irvin's p-curve in this impurity range.     

InP/InGaAs double-heterojunction bipolar transistors grown on (100)Si by metalorganic chemical vapor deposition

The authors report the successful fabrication of InP/InGaAs double-heterojunction bipolar transistors (DHBTs) grown by metalorganic chemical vapor deposition (MOCVD) on Si substrates. The Si substrates used were p-type (boron doped) FZ grown wafers with a resistivity of 5000 Ω×cm, oriented 2° off the (100) plane toward the [110] direction. Epitaxial layers for DHBTs were grown on the Si substrate with a thin GaAs buffer layer. A two-step growth process was applied for the InP layers on GaAs-on-Si wafers. The transistors exhibit high current gains over 200, which is comparable to those in transistors grown on InP substrates. The dislocations are found to increase the recombination current very little in the neutral base region, but increase in generation-recombination current at the emitter-base interface