An effective thermal circuit model for electro-thermal simulation of SOI analog circuits

A physics-based thermal circuit model is developed for electro-thermal simulation of SOI analog circuits. The circuit model integrates a non-isothermal device thermal circuit with interconnect thermal networks and is validated with high accuracy against finite element simulations in different layout structures. The non-isothermal circuit model is implemented in BSIMSOI to account for self-heating effect (SHE) in a Spice simulator, and applied to electro-thermal simulation of an SOI cascode current mirror constructed using different layouts. Effects of layout design on electric and thermal behaviors are investigated in detail. Influences of BOX thickness are also examined. It has been shown that the proposed non-isothermal approach is able to effectively account for influences of layout design, self-heating, high temperature gradients along the islands, interconnect temperature distributions, thermal coupling, and heat losses via BOX and interconnects, etc., in SOI current mirror structures. The model provides basic concepts and thermal circuits that can be extended to develop an effective model for electro-thermal simulation of SOI analog ICs.     

A novel nanoscale SOI MOSFET with Si embedded layer as an effective heat sink

A novel structure such as nanoscale silicon-on-insulator (SOI) MOSFET with silicon embedded layer (SEL-SOI) is proposed to reduce self-heating effects (SHEs) successfully. The SEL as a useful heat sink with high thermal conductivity is inserted inside the buried oxide. The SEL acts like a heat sink and is therefore easily able to distribute the lattice heat throughout the device. We noticed excellent improvement in the thermal performance of the device using two-dimensional and two-carrier device simulation. Our simulation results show that SHE has been dramatically reduced in the proposed structure. In regard to the simulated results, the SEL-SOI structure has shown good performance in comparison with the conventional SOI (C-SOI) structure when utilised in the high temperature applications.     

Equivalent circuit modeling of static substrate thermal coupling using VCVS representation

A new method is described which allows substrate thermal coupling between active devices to be accurately represented in a circuit simulation environment. The method, based on a substrate thermal equivalent circuit containing resistors and voltage-controlled voltage sources, allows for exact representation of substrate thermal coupling at any number of evaluation points. The topology of the equivalent circuit and derivation of its coefficients is described, and application of the technique to inter- and intradevice thermal effects is illustrated. The method is applied with a simple self-heating compact model representation to a measured GaAs device characteristic exhibiting gain collapse, and is found to accurately predict electrothermal behavior.     

DC/DC电源模块的有限元热分析

为解决电源模块的热可靠性问题,利用有限元热分析软件ANSYS对其进行热分析,得到整个模块的温度场分布情况;分析了模块中各生热元件的温升及其之间的热耦合情况;根据热分析结果提出热设计方法.最后,对模块各部分进行重新布局,证实了重新布局后的模块就其热可靠性而言更为合理.     

Scaling constraints imposed by self-heating in submicron SOIMOSFET's

The presence of a buried oxide layer in silicon causes enhanced self-heating in Silicon-On-Insulator (SOI) n-channel MOSFETs. The self-heating becomes more pronounced as device dimensions are reduced into the submicron regime because of increased electric field density and reduced silicon volume available for heat removal. Two-dimensional numerical simulations are used to show that self-heating manifests itself in the form of degraded drive current due to mobility reduction and premature breakdown. The heat flow equation was consistently solved with the classical semiconductor equations to study the effect of power dissipation on carrier transport. The simulated temperature increases in the channel region are shown to be in close agreement with recently measured data. Numerical simulation results also demonstrated accelerated turn-on of the parasitic bipolar transistor due to self-heating. Simulation results were used to identify scaling constraints caused by the parasitic bipolar transistor turn-on effect in SOI CMOS ULSI. For a quarter-micron n-channel SOI MOSFET, results suggest a maximum power supply of 1.8 V. In the deep submicron regime, SOI devices exhibited a negative differential resistance due to increased self-heating with drain bias voltage. Detailed comparison with bulk devices suggested significant reduction in the drain-source avalanche breakdown voltage due to increased carrier injection at the source-body junction     

Heat flow analysis for EOS/ESD protection device design in SOItechnology

Power-to-failure versus time-to-failure profiles for SOI protection devices are generated through a consideration of Joule heating. Experimental results are presented to justify assumptions made in the investigation of heat flow in SOI devices. A lossy transmission line equivalent model has been used to model the heat diffusion problem. A design space for multifinger NMOS protection devices has been developed on the basis of self-heating constraints. The method of images has been used to transform the multifinger device to an equivalent single-finger device to simplify the heat flow analysis     

A Nodal Model Dedicated to Self-Heating and Thermal Coupling Simulations

Both reduction in device sizes and enhanced increase in current densities lead to concern about the impact of the self-heating effect on device electrical characteristics. Moreover, in power transistors applications, devices are connected in parallel, so thermal interaction between devices also has to be considered. In this paper, a nodal model is proposed in order to take into account temperature variation due to self-heating and thermal coupling. This model associated with the HICUM Level 2 version 2.21 compact model is validated thanks to measurements made on specific test structures.     

Thermal analysis of AlGaN-GaN power HFETs

In this paper, we present a thermal analysis of AlGaN-GaN power heterojunction field-effect transistors (HFETs). We report the dc, small-signal, large-signal, and noise performances of AlGaN-GaN HFETs at high temperatures. The temperature coefficients measured for GaN HFETs are lower than that of GaAs pseudomorphic high electron-mobility transistors, confirming the potential of GaN for high-temperature applications. In addition, the impact of thermal effects on the device dc, small-signal, and large-signal characteristics is quantified using a set of pulsed and continuous wave measurement setups. Finally, a thermal model of a GaN field-effect transistor is implemented to determine design rules to optimize the heat flow and overcome self-heating. Arguments from a device, circuit, and packaging perspective are presented.     

Thermal and package performance limitations in LDMOSFET's for RFICapplications

This paper presents a systematic study of the limitations imposed by thermal and packaging considerations on radio-frequency (RF) performance of Si bulk and silicon-on-insulator (SOI) lateral DMOSFET's (LDMOSFET's). Several bulk and SOI devices are studied with the help of measurements as well as two-dimensional device simulations incorporating electrothermal models. Model parameters are extracted and used in circuit simulators to perform RF characterization of these devices. Further, a new three-region theory for the LDMOSFET is discussed and used to evaluate the static and RF performance of the devices in a nonisothermal environment. This paper shows that the package plays an important role in RF performance of SOI and bulk devices due to self-heating effects within the device. A detailed DC and RF performance evaluation is presented. Significant drift is observed in RF performance of bulk and SOI devices due to self-heating considerations. The physical understanding of these thermal effects within the device can facilitate the design of better packages for bulk and SOI devices     

Influence of lattice self-heating and hot-carrier transport ondevice performance

As device technologies improve, the traditional drift-diffusion transport model becomes inadequate to predict the performance of state-of-the-art semiconductor devices. The reasons are believed to be the larger field and field gradient inside advanced devices which cause lattice heating and hot carrier nonlocal transport phenomena. For more accurate prediction on device performance, a new device simulator capable of full thermodynamic simulation was developed. The carrier and carrier energy transport equations are directly derived from the Boltzmann transport equation, and the energy transfer among electrons, holes and crystal lattice takes into account most of the possible mechanisms. This simulator was used to simulate the DC behavior of a BJT and a half-micron NMOS. The simulation results show that for advanced devices, not only the drift-diffusion model becomes inadequate, but including only one of the two thermal effects results in error in simulated device characteristics     

新型SON器件的自加热效应

分析了自加热效应对SON器件性能的影响,并与SOI器件进行了比较．提出构造散热通路的方法来抑制SON器件的自加热效应,分析了不同通路情况对自加热效应的抑制程度．还对散热性能较好的具有不连续空洞埋层的SON器件进行了研究,并分析了空洞大小和横向位置偏差对器件性能的影响,为器件结构设计提供了指导．     

Two-dimensional simulation of thermal runaway in a nonplanarGTO-thyristor

The problem of electrothermal stability due to different cooling conditions has been investigated by computing the thermal transients in a nonplanar GTO-thyristor. In the first simulation, a steady state occurs with a heat sink removing all the dissipated power. In the second simulation severe thermal runaway is induced due to bad cooling conditions, allowing the analysis of destructive electrothermal interaction. The simulations are based on an advanced model for self-heating effects in silicon devices derived from first principles of irreversible thermodynamics. Self-consistently incorporating a phenomenological model of band gap narrowing in order to take account of heavy doping effects. The system of governing equations is valid in both the steady state and the transient regimes. Four characteristic effects contributing to the heat generation can be identified: Joule heating, recombination heating, Thomson heating, and carrier source heating. Thermal runaway is significantly accelerated in the simulations based on the thermodynamic model of thermoelectric transport compared to a conventional heuristic theory of thermoelectricity. The importance of the entropy balance equation is emphasized in order to derive the mathematical form of the heat flux and the current relations for electrons and holes. Limitations of underlying assumptions are discussed. It is shown that the heat generation implies the Thomson relations     

Thermalelectro-feedback model for multi-emitter finger power heterojunction bipolar transistor. Part I: Temperature profile

Poor thermal conductivity of GaAs, a self-heating phenomenon which results in the rapid rise of device temperature, is the major factor that limits and even degrades the electrical performance of GaAs-based heterojunction bipolar transistor (HBT) operated at high power densities. On the basis of this consideration, a numerical model is presented to study the interaction mechanism between the thermal and electrical behavior of AlGaAs/GaAs HBT with multiple-emitter fingers. The model mainly comprises a numerical model applicable for multi-finger HBT that solves the three-dimensional heat transfer equation. The device design parameters that influence the temperature profile and current distribution of the device are identified, and optimization concerning the device performance is made.     

Modeling of thermal behavior in SOI structures

Several physics-based analytical steady-state heat flow models for silicon-on-insulator (SOI) devices are presented, offering approaches at different levels of accuracy and efficiency for prediction of temperature profiles induced by power dissipated in SOI MOSFETs. The approaches are verified with the rigorous device simulation based on the energy transport model coupled with the heat flow equation. The models describe the one-dimensional temperature profile in the silicon film of SOI structure and two-dimensional heat flow in FOX, accounting for heat loss to the substrate via BOX and FOX, heat loss to (or gain from) interconnects, and heat exchanges between devices. These models are applied to investigate thermal behavior in single SOI devices and two-device SOI structures.     

Nanoscale electrothermal co-simulation: compact dynamic models of hyperbolic heat transport and self-consistent device Monte Carlo

Two problems in the self-consistent, electrothermal co-simulation of nanoscale devices, are discussed. It is shown that the construction of dynamic compact thermal models for nanoscale devices, based on solution of the hyperbolic (wavelike) heat transport equation, can follow essentially the same approach as the authors' analytical thermal impedance matrix method for the parabolic (diffusive) equation. The physicality of the hyperbolic equation is discussed in the light of calculated results. The analytical impedance matrix method for the time-independent case is employed in a thermally self-consistent device Monte Carlo simulation, illustrating the potential for detailed study of nanoscale electrothermal effects.     

Analysis of Self-Heating Effects in Ultrathin-Body SOI MOSFETs by Device Simulation

This paper discusses self-heating (SHE) effects in silicon-on-insulator (SOI) CMOS technology and applies device simulation to analyze the impact of thermal effects on the operation of nanoscale SOI n-MOSFETs. A 2-D drift-diffusion electrothermal simulation, using an electron transport model calibrated against Monte Carlo simulations at various temperatures, is employed in the analysis. We report the effects of device-structure parameters, such as SOI layer thickness, buried-oxide (BOX) thickness, source/drain (S/D) extension length, and thickness of the elevated S/D region, on the SHE of nanoscale MOSFETs. The SHE effects become significant due to the adoption of thin silicon layers and to the low thermal conductivity of the BOX, leading to the rise of large temperature under nominal operation conditions for high-performance digital circuits. The ac performance of SOI MOSFETs is influenced as well, and in particular, a severe degradation of the cutoff frequency of very short MOSFETs is predicted by numerical electrothermal device simulations. Although the effects of SHE on device performance are found to be somewhat modest and might be mitigated through device design, they may result in a degradation of the long-term reliability.     

基于Ansys优化模块的热设计应用

发热量大的电子器件温度会比较高,过高的温度会影响到器件的正常工作,因此需要用到热仿真软件去进行有效的热设计。优化设计是有限元分析软件(Ansys)的特有模块,利用该模块应用于两种典型的热设计实例,分别是处理器CPU散热器结构和电路板器件分布的优化设计,仿真分析出来的结果显示,CPU散热器的散热性能得到明显的提高,电路板上各器件的温度均得到降低,获得良好的优化效果。     

Simulating the dynamic electrothermal behavior of power electroniccircuits and systems

The simulator solves for the temperature distribution within the semiconductor devices, packages, and heat sinks (thermal network) as well as the currents and voltages within the electrical network. The thermal network is coupled to the electrical network through the electrothermal models for the semiconductor devices. The electrothermal semiconductor device models calculate the electrical characteristics based on the instantaneous value of the device silicon chip surface temperature and calculate the instantaneous power dissipated as heat within the device. The thermal network describes the flow of heat from the chip surface through the package and heat sink and thus determines the evolution of the chip surface temperature used by the semiconductor device models. The thermal component models for the device silicon chip, packages, and heat sinks are developed by discretizing the nonlinear heat diffusion equation and are represented in component form so that the thermal component models for various packages and heat sinks can be readily connected to one another to form the thermal network     

Efficient thermal modeling of SOI MOSFETs for fast dynamic operation

An efficient dynamic thermal model has been developed for silicon-on-insulator (SOI) MOSFETs. The model is derived from the variational principle using a thermal functional, and is able to describe extremely fast dynamic thermal behavior in SOI devices subjected to sudden changes in power generation. The developed model is further converted into a thermal circuit with time-varying thermal resistances and capacitances. With the circuit implemented in a circuit simulator, these time-varying thermal resistances and capacitances are able to reasonably capture extremely fast temperature evolution in SOI devices without including a large number of nodes. The developed dynamic thermal model and circuit are verified with the rigorous device simulation including self-heating.