低功耗精密电源监控电路设计与开发

电源监控电路的主要功能是上电或电源电压低于设门限时产生复位输出，保证单片机在电源电压、系统时钟稳定可靠的前提下工作。设计了一种以低温票带隙基准为核心的电压检测电路，包括电源比较电路、带隙比较器、可调电压失效比较器、振荡器、计数器和数字控制逻辑，用于实现上电复位和欠压保护。经过仿真证明该电路阈值电压随温度变化小，性能稳定可靠，并且具有低功耗和高精度的特点。     

适用于1000Base-T以太网的低抖动低功耗频率综合器

采用高速鉴频鉴相器(TSPC)、经典抗抖动的电荷泵、交叉耦合差分延迟单元以及电阻分压相位内插电路等结构设计了一个应用于1000Base-T以太网收发器的频率综合器电路,并能兼容10/100Mbps模式.该电路同时满足发送电路上升下降斜率控制和时钟恢复电路对于多相时钟(128相)的需要,大大节约了面积和功耗.在晶振的绝对抖动σ约为16ps情况下,输出25MHz测试时钟信号σ仅为11ps.表明该频率综合器有较强的抑制噪声能力,能很好满足发送和接收电路对于时钟性能的要求.芯片采用SMIC 0.18μm的标准CMOS工艺,电源电压为1.8V,功耗小于4mW.     

适用于1000Base-T以太网的低抖动低功耗频率综合器

采用高速鉴频鉴相器(TSPC)、经典抗抖动的电荷泵、交叉耦合差分延迟单元以及电阻分压相位内插电路等结构设计了一个应用于1000Base-T以太网收发器的频率综合器电路,并能兼容10/100Mbps模式.该电路同时满足发送电路上升下降斜率控制和时钟恢复电路对于多相时钟(128相)的需要,大大节约了面积和功耗.在晶振的绝对抖动σ约为16ps情况下,输出25MHz测试时钟信号σ仅为11ps.表明该频率综合器有较强的抑制噪声能力,能很好满足发送和接收电路对于时钟性能的要求.芯片采用SMIC 0.18μm的标准CMOS工艺,电源电压为1.8V,功耗小于4mW.     

一种用于电子标签的低功耗高精度时钟电路设计

设计了一种适合射频电子标签的高精度时钟产生电路,在分析影响输出频率稳定性各因素的基础上,针对标签电路低功耗宽工作环境的要求,提出一种全CMOS结构带隙基准做偏置的电流受限型环形振荡器.全MOS自偏置PTAT迁移率和阈值电压互补偿带隙基准源的设计,使时钟电路受电源电压和温度的影响极小.全电路采用TSMC 0.18 μm CMOS工艺实现.HSpice仿真结果表明:电源电压为1.2～2 V,温度从-10～ 70 ℃变化时,带隙基准温度系数和电源电压抑制比分别为12 ppm/℃和59 dB,时钟稳定度在±2.5%以内,电路平均功耗仅为4 μw.     

一种适用于心电信号检测的斩波前置放大器

提出一种适合心电信号检测的低压、低功耗、低噪声、高共模抑制比的差分差值斩波前置放大器,包括偏置电路、主放大电路和时钟产生电路,其中,时钟产生电路包括张弛振荡器和两相非交叠时钟产生电路。该放大器采用斩波技术减小了低频1/f噪声,采用差分差值输入、交叉耦合结构增加了共模抑制比,采用T型电容反馈减小了芯片面积,优化了放大器性能。芯片采用SMIC 0.18 μm 1P6M CMOS工艺设计,使用PSS,PAC,PNOISE进行仿真分析。结果表明,放大器在1.8 V电源电压下,静态电流为35 μA,闭环增益为40.6 dB,共模抑制比为115 dB,输入等效噪声仅为950 nV(rms)(0.01~100 Hz),适用于心电信号检测领域。     

高电源抑制比带隙基准电压源的设计

提出一种采用0.25 μm CMOS工艺的低功耗、高电源抑制比、低温度系数的带隙基准电压源(BGR)设计.设计中,采用了共源共栅电流镜结构,运放的输出作为驱动的同时也作为自身电流源的驱动,并且实现了与绝对温度成正比(PTAT)温度补偿.使用Hspice对其进行仿真,在中芯国际标准0.25 μm CMOS工艺下,当温度变化范围在-25～125℃和电源电压变化范围为4.5～5.5 V时,输出基准电压具有9.3×10-6 V/℃的温度特性,Vref摆动小于0.12 mV,在低频时具有85 dB以上的电源电压抑制比(PSRR),整个电路消耗电源电流仅为20μA.     

一种高电源抑制比的CMOS带隙基准电压源设计

介绍一种基于CSMC0.5μm工艺的低温漂高电源抑制比带隙基准电路。本文在原有Banba带隙基准电路的基础上,通过采用共源共栅电流镜结构和引入负反馈环路的方法,大大提高了整体电路的电源抑制比。Spectre仿真分析结果表明:在-40~100℃的温度范围内,输出电压摆动仅为1.7 mV,在低频时达到100 dB以上的电源抑制比(PSRR),整个电路功耗仅仅只有30μA。可以很好地应用在低功耗高电源抑制比的LDO芯片设计中。     

改进结构的低压低功耗CMOS带隙基准源

提出了一种低电压、低功耗、中等精度的带隙基准源,针对电阻分流结构带隙基准源在低电源电压下应用的不足作出了一定的改进,整体电路结构简单且便于调整,同时尽可能地减少了功耗.该电路采用UMC 0.18 μm Mixed Mode 1.8 V CMOS工艺实现.测试结果表明,电路在1 V电源电压下,在-20～30℃的温度范围内,基准电压的温度系数为20×10-6/℃,低频时的电源电压抑制比为-54 dB,1 V电源电压下电路总功耗仅为3μW.     

基于DLL的1.25G超宽带通信系统时钟生成电路

设计并实现了一个基于延时锁定环(DLL)、用于超宽带(UWB)无线通信系统的1.25GHz时钟生成电路。该时钟生成电路由两个DLL和一个自调谐LC滤波电路组成,输入125MHz的参考时钟,输出1.25GHz的差分时钟和间隔100ps的16相时钟。通过优化电荷泵电路有效地减小了静态相位误差,新式自调谐LC滤波电路的应用消除了工艺偏差对谐振的影响。在1.8V电源电压,SMIC0.18μmCMOS工艺下,该时钟生成电路在各种工作条件下均表现出良好的性能,在标准情况下静态相位误差仅为9ps,最大时钟抖动为10ps。当电感存在30%的工艺偏差时,滤波电路的谐振频率能够自动维持在1.25GHz上。     

面向压电能量收集的传感器自供电电源设计

随着物联网传感器网络的快速发展,微弱能量收集电路因其诸多优越性而备受关注。该文设计了一种基于压电能量收集技术的电路,其通过收集环境中的低频机械振动能量,经压电陶瓷(PZT)换能器产生交流电压,再经四倍压电路放大,并通过LTC3588-1电源管理电路整流变换,最终产生一个可供低功耗传感器工作的可切换的标准电压。实验结果表明,该电路可有效支持低功耗传感器正常工作。     

Real-time programmable low power SC bandpass filter

A real-time programmable switched capacitor (SC) second-order bandpass filter is presented. It is based on the voltage inverter switch (VIS) principle using inverse recharging devices. These devices are realized with dynamic amplifiers in order to achieve low power dissipation. The filter contains only grounded or virtually grounded network capacitances and, therefore, it is insensitive to the parasitic capacitances between the bottom plate of the implemented MOS capacitors and the substrate. The circuit offers digital programming capability (two Q factors and three center frequencies) and low power dissipation (185 /spl mu/W at a sampling frequency of 8 kHz and with a power supply voltage of 10 V). The filter has been integrated in CMOS metal-gate technology.     

New analogue four-quadrant voltage divider

A new circuit structure for the realisation of an analogue four-quadrant voltage divider with improved dynamic performance is proposed. The structure was developed on the basis of the augmented Lagrangian method and the gradient optimisation approach. The circuit is especially suited for monolithic IC implementation by employing the CMOS switched-capacitor (SC) techniques. The device has been built using SC discrete components and also simulated on computer. Experimental test and computer simulation results have confirmed the theoretical predictions, especially the dynamic error reduction of the device.<>     

Low-voltage high-speed switched-capacitor circuits without voltage bootstrapper

Low-voltage high-speed switched-capacitor (SC) circuit design without using voltage bootstrapper is presented. The basic building block used for low-voltage SC circuit design is the auto-zeroed integrator (AZI), which can work at both low voltage and high sampling frequency. With this method, two low-voltage SC systems were successfully designed and implemented in 1.2-/spl mu/m CMOS technology. The first one is a fully differential SC bandpass biquad working at 1.5 V and 5.0-MHz clock frequency. The measured Q value is 8.0 at the center frequency of 833 kHz. The second one is a fully differential fourth-order bandpass /spl Delta//spl Sigma/ modulator that also works at 1.5 V and 5.0 MHz. Its measured third-order intermodulation is less than -78 dBc due to the low distortion characteristic of AZI. The measured signal-to-noise ratio of the modulator is 61 dB within the narrow band of 25 kHz centered at 1.25 MHz.     

Endothelial cell electrical impedance parameter artifacts produced by a gold electrode and phase sensitive detection

Frequency dependent cellular micro-impedance estimates obtained from a gold two-electrode configuration using phase sensitive detection have become increasingly used to evaluate cellular barrier model parameters. The results of this study show that cellular barrier function parameter estimates optimized using measurements obtained from this biosensor are highly susceptible to both time dependent and systematic instrumental artifacts. Based on a power spectral analysis of experimentally measured microelectrode voltages, synchronous, 60 Hz, and white Gaussian noise were identified as the most significant time dependent instrumental artifacts. The reduction of these artifacts using digital filtering produced a corresponding reduction in the optimized model parameter fluctuations. Using a series of instrumental circuit models, this study also shows that electrode impedance voltage divider effects and circuit capacitances can produce systematic deviations in cellular barrier function parameter estimates. Although the implementation of an active current source reduced the voltage divider effects, artifacts produced by coaxial cable and other circuit capacitive elements at frequencies exceeding 1 kHz still remained. Reducing time dependent instrumental fluctuations and systematic errors produced a significant reduction in cellular model barrier parameter errors and improved the model fit to experimental data.     

Transformerless DC-to-DC converters with large conversion ratios

A novel switching DC-to-DC converter is introduced in which large voltage step-down ratios can be achieved without a very small duty ratio and without a transformer. The circuit is an extension of the Cuk converter to incorporate a multistage capacitor divider. A particularly suitable application would be a 50 V to 5 V converter in which DC isolation is not required. The absence of a transformer and a larger duty ratio permits operation at a high switching frequency and makes the circuit amenable to partial integration and hybrid construction techniques. An experimental 50 W three-stage voltage divider Cuk converter converts 50 V to 5 V at 500 kHz, with an efficiency higher than that for a basic Cuk converter operated at the same conditions. A corresponding voltage-multiplier Cuk converter is described, as well as dual buck-boost-derived step-down and step-up converters     

Self-commutated auxiliary circuit ZVT PWM converters

This paper introduces a novel class of zero voltage transition (ZVT) DC/DC pulse-width modulation (PWM) converters that use a resonant inductance-capacitance (L-C) circuit connected to the auxiliary switch, which is termed a self-commutated auxiliary circuit. It provides a simple and reliable means of achieving zero-current conditions (ZCS) for auxiliary switch commutations under wide line and load ranges, without the inclusion of any kind of DC voltage source. Furthermore, this auxiliary circuit is placed in parallel with the main power converter, retaining the ZVT characteristics. The self-commutated auxiliary circuit ZVT PWM boost is analyzed, and its feasibility and reliability are confirmed by experimental results obtained from laboratory prototypes rated at 1 kW and 100 kHz.     

Superintegrated voltage clamp

A monolithic implementation of a voltage clamp circuit is described that saves area and reduces capacitance, as the transistor and the voltage divider resistor required are merged into a single device. Following this principle in current switch logic circuits, even the emitter follower can be superintegrated into the collector loads. Moreover, base-bleeding resistors can be incorporated in transistors of silicon-controlled rectifiers.     

Design of C-testable DCVS binary array dividers

Clocked differential cascode voltage switch (DCVS) circuits are dynamic CMOS circuits that have the advantage of being protected against test-set invalidation due to circuit delays and timing skews. The problem of testing nonrestoring and restoring DCVS binary array dividers is discussed. It is shown that a DCVS nonrestoring array divider can be made C-testable with only four or five vectors. These vectors detect all the detectable single stuck-at, stuck-open, and stuck-on faults in the circuit. The additional hardware required to achieve C-testability for an n×n nonrestoring array divider only consists of n-1 two-input XOR gates and one control input. It is also shown that a restoring DCVS binary array divider can be made C-testable with only six vectors, which also detect all the detectable single stuck-at, stuck-open, and stuck-on faults in the circuit. The hardware overhead required for the C-testable design of the n×n restoring array divider consists of n two-input XOR gates and one control input     

Ka波段具有宽锁定范围高注入灵敏度的分频器*

This paper proposes a direct injection-locked frequency divider（ILFD） with a wide locking range in the Ka-band. A complementary cross-coupled architecture is used to enhance the overdriving voltage of the switch transistor so that the divider locking range is extended efficiently. New insights into the locking range and output power are proposed. A new method to analyze and optimize the injection sensitivity is presented and a layout technique to reduce the parasitics of the cross-coupled transistors is applied to decrease the frequency shift and the locking range degradation. The circuit is designed in a standard 90-nm CMOS process. The total locking range of the ILFD is 43.8% at 34.5 GHz with an incident power of –3.5 dBm. The divider IC consumes 3.6 mW of power at the supply voltage of 1.2 V. The chip area including the pads is 0.50.5 mm2.     

A self-timed divider using a new fast and robust pipeline scheme

This paper investigates the potential of self-timed property of differential cascode voltage switch logic (DCVSL) circuits, and examines architectural techniques for achieving self-timing in DCVSL circuits. As a result, a fast and robust handshake scheme for dynamic asynchronous circuit design is proposed. It is novel and more general than other similar schemes. The proposed self-timed datapath scheme is verified by an 8-bit divider which is implemented using AMS 0.6-μm CMOS technology, and the chip size is about 1.66 mm×1.70 mm. The chip testing results show that the divider functions correctly and the latency for 8-bit quotient-digit generation is 17 ns (about 58.8 MHz)