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FAN Xiumei CHEN Hui 《电子学报:英文版》2008,(4):698-702
Delay-tolerant networks (DTNs) routing can be divided into three types:message-replication-based, network-knowledge-based, and network-coding-based. In this paper, we design replication-based protocol and use the forwarded history of messages at nodes for them to make asynchronous routing decision. We called it Forwarded history-based (FH) algorithm. FH only selects a subset of relay node candidates as the potential carriers of a message in order to decrease the total traffic generated by message replication. Simulation results are used to establish the effectiveness of the FH algorithm. 相似文献
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In this article, a new system model for sphere decoding (SD) algorithm is introduced. For the 2 × 2 multipleinput multiple-out (MIMO) system, a simplified maximum likelihood (SML) decoding algorithm is proposed based on the new model. The SML algorithm achieves optimal maximum likelihood (ML) performance, and drastically reduces the complexity as compared to the conventional SD algorithm. The improved algorithm is presented by combining the sphere decoding algorithm based on Schnorr-Euchner strategy (SE-SD) with the SML algorithm when the number of transmit antennas exceeds 2. Compared to conventional SD, the proposed algorithm has low complexity especially at low signal to noise ratio (SNR). It is shown by simulation that the proposed algorithm has performance very close to conventional SD. 相似文献
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Xu Zhanqi Yi Kechu Liu Zengji 《电子科学学刊(英文版)》2006,23(4):528-531
Derived from a proposed universal mathematical expression, this paper investigates a novel algorithm for parallel Cyclic Redundancy Check (CRC) computation, which is an iterative algorithm to update the check-bit sequence step by step and suits to various argument selections of CRC computation. The algorithm proposed is quite suitable for hardware implementation. The simulation implementation and performance analysis suggest that it could efficiently speed up the computation compared with the conventional ones. The algorithm is implemented in hardware at as high as 21Gbps, and its usefulness in high-speed CRC computations is implied, such as Asynchronous Transfer Mode (ATM) networks and 10G Ethernet. 相似文献
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XiKang GeNing FengChongxi 《电子科学学刊(英文版)》2003,20(3):215-219
Multi-service SDH networks support both packet-and circuit-switched traffic.Optimal design of such a network means to guarantee the circuit connections and configure a logical packet-switched topology with lowest congestion.This letter first formulates the problem as a mixed integer linear programming,which achieves optimal solution but has high computation.Then a heuristic algorithm is proposed to yield near-optimal soultion effciently.Performance of the algorithm is verified by an example. 相似文献
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Network virtualization is a promising way to overcome the current ossification of the Intemet. It is essential challenge to find effective, efficient and robust embedding algorithms for recovering virtual network. The virtual network mapping algorithm based on integer programming which was proposed months ago. But it did consider the faults of physical network resources, which is so called survivable virtual network embedding (VNE) problem. Previous strategies for enabling survivability in network virtualization focused on providing protection for the physical network or enhancing the virtual networks by providing backup physical resources in advance, and treated all the physical failures as link failures. In the article, a dynamic recovery method is proposed to solve the survivable virtual network embedding problem based on the integer programming VNE algorithm. The dynamic recovery method doesn't need to backup physical resources and it makes more substrate resources which can be used in the embedding. The dynamic recovery process will be activated only when physical failures occur. Different algorithms are used to recovery node and link failures. Simulations show that the method helps to recover almost all of physical failures by finding the substitute nodes and paths, and its performance is very close to that of pure VNE method without considering physical failures. 相似文献
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Study on Optimizing of Ball Passing Strategy and Role Switching Mechanism for Robot Soccer 总被引:2,自引:0,他引:2
HAN Li-dong FAN Shou-wen 《中国电子科技》2006,4(1):80-85
A new ball passing strategy for robot soccer is proposed in this paper. With introduce of a new algorithm on ball passing, the optimum strategy is confirmed to be more efficient and exact when passing a ball. Questions of role switching in multi-intelligent agent cooperation in robot soccer are described based on Generalized Stochastic Petri-Net (GSPN). Results of computer simulation have confirmed the feasibility and efficiency of above Petri-net method. 相似文献
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Amdahl's law is a simple and fundamen- tal tool for understanding the evolution of performance as a function of parallelism. Following a recent trend on timing and power analysis of general purpose many-core chip using this law, we develop a novel PIPP analytical model for evaluating the performance and power of hier- archical on-chip large-scale parallel architectures with the core number, super-node size, processing element number, and function unit number taken into consideration. We thereby investigate the influence of workload characteris- tics (Thread-level parallel TLP, Instruction-level parallel ILP and Data-level parallel DLP) on resource allocation with the restriction of performance and power. The re- sults provide some feasible options to design TOPS level DSP architecture as well as a theoretical basis for making the design more scalable. 相似文献
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Block diagonalization (BD) is an efficient precoding technique that eliminates inter-user interference in downlink multiple-input multiple-output (MIMO) systems. User selection strategies applied to multiuser MIMO systems with BD are investigated in this article. To enhance the capacity of multiuser MIMO systems, an equivalent capacity maximum (ECM) user selection strategy is proposed with low computational complexity. Considering both the factors of channel correlations and channel conditions, the proposed strategy can select a group of users to serve for maximizing the total throughput. Simulation results indicate that, for various channel conditions, proposed ECM strategy gains a better performance compared with traditional user selection strategies, and achieves a near optimal throughput as the exhaustive search. 相似文献
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Aiming to realize fast and accurate fault diagnosis in complex network environment, this article proposes a set of anomaly detection algorithm and intelligent fault diagnosis model. Firstly, a novel anomaly detection algorithm based on time series analysis is put forward to improve the generalized likelihood ratio (GLR) test, and thus, detection accuracy is enhanced and the algorithm complexity is reduced. Secondly, the intelligent fault diagnosis model is established by introducing neural network technology, and thereby, the anomaly information of each node in end-to-end network is integrated and processed in parallel to intelligently diagnose the fault cause. Finally, server backup solution in enterprise information network is taken as the simulation scenario. The results demonstrate that the proposed method can not only detect fault occurrence in time, but can also implement online diagnosis for fault cause, and thus, real-time and intelligent fault management process is achieved. 相似文献
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基于现代计算机的多级存储结构,采用消息传递并行编程模型对格子Boltzmann并行程序进行了Cache优化.实验结果表明,优化后的程序能够减少80%的Cache缺失,性能提高20%,而且经过预处理的并行程序性能也有很大提高. 相似文献
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并行程序执行的不确定性给并行程序的开发、调试和测试带来了挑战,严重阻碍了并行软件的发展。确定性并行编程模型是保证并行程序确定性的途径之一,但是程序可能因保证确定性而带来性能损失。文章以dedup基准程序为案例,探索确定性共享内存并行编程模型DetSM下的任务调度策略。文章首先分析了原dedup的程序架构和调度模型,然后结合DetSM的特点,将两种确定性的调度策略--"轮询"和"一对一"相结合来设计适合本应用的任务调度策略。实验结果表明,本文最后改进的调度策略是很有效的,它使得改写的dedup在性能上可以和原dedup相比较,甚至超越原dedup。 相似文献
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实时图像处理并行操作系统的微内核设计和实现 总被引:6,自引:0,他引:6
本文主要设计和实现了运行在数字信号处理阵列上支持中高层图像处理的实时图像处理并行操作系统(RTIPPOS)微内核,该内核提供了任务分解模型,并发进程管理,支持局部消息传递,同步,设计了快速共享消息传递方式和它辅助性能,内核原语支持POSIX系统调用的C语言接口和抽象级的用户封装,有行为的高效性和预测性,本文是对RTIPPOS微内核设计的综述。 相似文献
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研究并实现了三维电与磁本构参数均为各向异性介质时的时域有限差分(ANI-FDTD)并行算法.根据电磁各向异性介质时域有限差分(ANI-FDTD)迭代式,电场和磁场某一节点场值的计算均涉及到其周围邻近28个场分量节点值.详细分析了该情况下各向异性介质时域有限差分(ANI-FDTD)并行算法中的数据通讯规律.通过采用相邻子域重叠半个网格的区域划分方式,传递分界面两边相关节点的场值,实现了局域网内各节点机的协同并行计算.数值计算结果表明了该算法和程序的正确性. 相似文献
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The EM algorithm for PET image reconstruction has two major drawbacks that have impeded the routine use of the EM algorithm: the long computation time due to slow convergence and a large memory required for the image, projection, and probability matrix. An attempt is made to solve these two problems by parallelizing the EM algorithm on multiprocessor systems. An efficient data and task partitioning scheme, called partition-by-box, based on the message passing model is proposed. The partition-by-box scheme and its modified version have been implemented on a message passing system, Intel iPSC/2, and a shared memory system, BBN Butterfly GP1000. The implementation results show that, for the partition-by-box scheme, a message passing system of complete binary tree interconnection with fixed connectivity of three at each node can have similar performance to that with the hypercube topology, which has a connectivity of log(2) N for N PEs. It is shown that the EM algorithm can be efficiently parallelized using the (modified) partition-by-box scheme with the message passing model. 相似文献
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Low-density parity-check (LDPC) codes, proposed by Gallager, emerged as a class of codes which can yield very good performance on the additive white Gaussian noise channel as well as on the binary symmetric channel. LDPC codes have gained lots of importance due to their capacity achieving property and excellent performance in the noisy channel. Belief propagation (BP) algorithm and its approximations, most notably min-sum, are popular iterative decoding algorithms used for LDPC and turbo codes. The trade-off between the hardware complexity and the decoding throughput is a critical factor in the implementation of the practical decoder. This article presents introduction to LDPC codes and its various decoding algorithms followed by realisation of LDPC decoder by using simplified message passing algorithm and partially parallel decoder architecture. Simplified message passing algorithm has been proposed for trade-off between low decoding complexity and decoder performance. It greatly reduces the routing and check node complexity of the decoder. Partially parallel decoder architecture possesses high speed and reduced complexity. The improved design of the decoder possesses a maximum symbol throughput of 92.95 Mbps and a maximum of 18 decoding iterations. The article presents implementation of 9216 bits, rate-1/2, (3, 6) LDPC decoder on Xilinx XC3D3400A device from Spartan-3A DSP family. 相似文献