共查询到20条相似文献,搜索用时 78 毫秒
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双向负阻晶体管的脉冲应用高广和,冯明昭,付连生关键词负阻晶体管,阶跃二极管,亚钠秒脉冲1引言双向负阻晶体管(BNRT)是我国发明的一种新功能器件,该器件是一种合并晶体管结构,如图1(a)所示,它在电路中的符号参照图1(b)。两输出电极El和E2具有完... 相似文献
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三端电压控制型负阻器件(6)郭维廉(天津大学电子工程系300072)第六章新型“∧”负阻晶体管[21]新型“∧”负阻晶体管(NewLambdaNegative-ResistanceTransistor),简称NLNRT,是近几年来新提出的一种三端负阻... 相似文献
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光电负阻晶体管的初步研究 总被引:12,自引:1,他引:11
本文对“λ”双极晶体管型光电负阻晶体管,首次给出了完整的等效电路,并以此等效电路为基础,用PSPICE电路模拟程序,对PLBT的Iph-VcE特性进行了模拟。模拟结果与从PLBT实验性器件实测的Iph-VCE特性吻合得很好,初步研究还表明,此器件除了作为光探测器外,还具有光生振荡和光控调频等功能。 相似文献
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三端电压控制型负阻器件(2)郭维廉(天津大学电子工程系300072)第二章表面控制负阻晶体管(NEGIT)[5]表面控制负阻晶体管(Surface-ControlledNesativeImpedandeTransistor),简称NEGIT是在栅控晶... 相似文献
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光电双向负阻晶体管(PBNRT)是一种新型S型光电负阻器件.本文对它的光电负阻特性进行了数值模拟和实验研究,给出了器件等效电路.PBNRT在光电混合工作模式下具有光控电流开关效应,可通过光照和控制电压两种控制方式改变器件的S型负阻特性.模拟和实验结果均表明:光照强度增大,维持电压基本保持不变,转折电压减小,负阻电压摆幅减小;而增大控制电压,维持电压和转折电压均增大,输出负阻特性曲线右移.上述特点使得PBNRT可望在光电开关、光控振荡和光电探测等方面有很好的应用前景. 相似文献
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An optically controlled SiC/SiCGe lateral power transistor based on superjunction structure has been proposed, in which n-SiCGe/p-SiC superjunction structure is employed to improve device figure of merit. Performance of the novel optically controlled power transistor was simulated using Silvaco Atlas tools, which has shown that the device has a very good response to the visible light and the near infrared light. The optoelectronic responsivities of the device at 0.5 μm and 0.7 μm are 330 mA/W and 76.2 mA/W at 2 V based voltage, respectively. 相似文献
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达林顿管是一种两级或多级的复合管。功率型的达林顿管的功率级是后极,而后极功率管的δVbe不能直接测量,所以,达林顿管瞬态热阻测量仪器的研发一直是一个的难点。从晶体管的瞬态热阻测量原理出发,研究了达林顿管的热阻测量方法。此方法也可以引申到达林顿管稳态热阻的检测中。 相似文献
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A solvent-free lift-off method has been introduced to fabricate the aluminum nano-hole array with diameter down to 80 nm as the base electrode for a vertical organic transistor. The imprinted vertical organic transistor exhibited base leakage current density as low as 5 × 10−5 mA/cm2 and high ON/OFF current ratio as high as 105. 相似文献
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Yu-Hsin Lin Yu-Fan Chang Hsin-Fei Meng Hsiao-Wen Zan Wensyang Hsu Chao-Hsuan Chen 《Organic Electronics》2013,14(11):3052-3060
The vertical organic space-charge-limited transistor made of P3HT and small-molecule phosphorescent organic light-emitting diode (OLED) are made on two separate glass substrate by blade coating, then soldered vertically together by tin balls with 40 μm diameter. The soldering is done by hot wind of 150 °C for 5 min Contact resistance is only 10 Ω. The vertical transistor is annealed at 150 °C for 5 min before soldering to enhance the output current up to 25 mA/cm2 and give high thermal stability. Both OLED and the annealed vertical transistor are not affected by the soldering process. The vertical transistor has 1/4 of the OLED area and turns on the bottom-emission white OLED up to 300 cd/m2 and orange OLED up to 600 cd/m2. The entire operation is within 8 V. OLED and transistor array can therefore be made on separate glass substrates then soldered together to form the display. 相似文献
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Yen-Chu Chao Kai-Ruei Wang Hsin-Fei Meng Hsiao-Wen Zan Yung-Hsuan Hsu 《Organic Electronics》2012,13(12):3177-3182
In this work, we proposed a fast and controllable blade coating process to form non-close-packed nanosphere structures. We investigated the key to obtain well-distributed non-close-packed PS spheres with blade coating. We utilized the blade-coated nanosphere structure to realize colloidal lithography and fabricate a vertical channel polymer transistor, the space-charge-limited transistor (SCLT). We demonstrated that SCLT utilizing blade-coated nanospheres delivered 13.9 mA/cm2 at 1.8 V with an on/off current ratio as 45,000. The process of blade-coating nanospheres may facilitate the commercialization of low-cost colloidal lithography. 相似文献
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采用国产的4H-SiC外延材料和自行开发的SiC双极晶体管的工艺技术,实现了4H-SiC npn双极晶体管特性。为避免二次外延或高温离子p+注入等操作,外延形成n+/p+/p/n-结构材料,然后根据版图设计进行相应的刻蚀,形成双台面结构。为保证p型基区能实现良好的欧姆接触,外延时在n+层和p层中间插入适当高掺杂的p+层外延,但也使双极晶体管发射效率降低,电流放大系数降低。为提高器件的击穿电压,在尽量实现低损伤刻蚀时,采用牺牲氧化等技术减少表面损伤及粗糙度,避免表面态及尖端电场集中,并利用SiC能形成稳定氧化层的优势来形成钝化保护。器件的集电结反向击穿电压达200 V,集电结在100 V下的反向截止漏电流小于0.05 mA,共发射极电流放大系数约为3。 相似文献
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Byoung Gun Choi Seok‐Bong Hyun Geum‐Young Tak Hee‐Tae Lee Seong‐Su Park Chul Soon Park 《ETRI Journal》2005,27(5):579-584
A CMOS direct‐conversion mixer with a single transistor‐level topology is proposed in this paper. Since the single transistor‐level topology needs smaller supply voltage than the conventional Gilbert‐cell topology, the proposed mixer structure is suitable for a low power and highly integrated RF system‐on‐a‐chip (SoC). The proposed direct‐conversion mixer is designed for the multi‐band ultra‐wideband (UWB) system covering from 3 to 7 GHz. The conversion gain and input P1dB of the mixer are about 3 dB and ?10 dBm, respectively, with multi‐band RF signals. The mixer consumes 4.3 mA under a 1.8 V supply voltage. 相似文献