A 0.13μm CMOS Δ ∑ fractional-N frequency synthesizer for WLAN transceivers

A fractional-N frequency synthesizer fabricated in a 0.13μm CMOS technology is presented for the application of IEEE 802.11 b/g wireless local area network(WLAN) transceivers.A monolithic LC voltage controlled oscillator(VCO) is implemented with an on-chip symmetric inductor.The fractional-TV frequency divider consists of a pulse swallow frequency divider and a 3rd-order multistage noise shaping(MASH)△Σmodulator with noise-shaped dithering techniques.Measurement results show that in all channels,phase noise of the synthesizer achieves -93 dBc/Hz and -118 dBc/Hz in band and out of band respectively with a phase-frequency detector (PFD) frequency of 20 MHz and a loop bandwidth of 100 kHz.The integrated RMS phase error is no more than 0.8°.The proposed synthesizer consumes 8.4 mW from a 1.2 V supply and occupies an area of 0.86 mm~2.     

A 1.2-V, 84-dB Σ△ ADM in 0.18-μm digital CMOS technology

A low power and low voltage∑△analog-to-digital modulator is realized with digital CMOS technology, which is due to full compensated depletion mode capacitors.Compared with mixed signal technology,this type of modulator is more compatible for pure digital applications.A pseudo-two-stage class-AB OTA is used in switchedcapacitor integrators for low voltage and low power.The modulator is realized in standard SMIC 0.18μm 1P6M digital CMOS technology.Measured results show that with 1.2 V supply voltage and a 6 MHz sample clock,the dynamic range of the modulator is 84 dB and the total power dissipation is 2460μW.     

A fractional-N frequency divider for multi-standard wireless transceiver fabricated in 0.18 μm CMOS process

With the rapid evolution of wireless communication technology,integrating various communication modes in a mobile terminal has become the popular trend.Because of this,multi-standard wireless technology is one of the hot spots in current research.This paper presents a wideband fractional-N frequency divider of the multi-standard wireless transceiver for many applications.High-speed divider-by-2 with traditional sourcecoupled-logic is designed for very wide band usage.Phase switching technique and a chain of divider-by-2/3 are applied to the programmable frequency divider with 0.5 step.The phase noise of the whole frequency synthesizer will be decreased by the narrower step of programmable frequency divider.△-Σ modulator is achieved by an improved MASH 1-1-1 structure.This structure has excellent performance in many ways,such as noise,spur and input dynamic range.Fabricated in TSMC 0.18 μm CMOS process,the fractional-N frequency divider occupies a chip area of 1130 × 510μm2 and it can correctly divide within the frequency range of 0.8-9 GHz.With 1.8 V supply voltage,its division ratio ranges from 62.5 to 254 and the total current consumption is 29 mA.     

A 55 nm CMOS △∑fractional-N frequency synthesizer for WLAN transceivers with low noise filters

A fully integrated ΔΣ fractional-N frequency synthesizer fabricated in a 55 nm CMOS technology is presented for the application of IEEE 802.11b/g wireless local area network(WLAN) transceivers.A low noise filter,occupying a small die area,whose power supply is given by a high PSRR and low noise LDO regulator,is integrated on chip.The proposed synthesizer needs no off-chip components and occupies an area of 0.72 mm2 excluding PAD.Measurement results show that in all channels,the phase noise of the synthesizer achieves -99 dBc/Hz and -119 dBc/Hz in band and out of band respectively with a reference frequency of 40 MHz and a loop bandwidth of 200 kHz.The integrated RMS phase error is no more than 0.6°.The proposed synthesizer consumes a total power of 15.6 mW.     

A fractional-N frequency synthesizer-based multi-standard I/Q carrier generation system in 0.13μm CMOS

This paper proposes a sigma-delta fractional-N frequency synthesizer-based multi-standard I/Q carrier generation system.With reasonable frequency planning,the system can be used in multi-standard wireless communication applications(GSM,WCDMA,GPRS,TD-SCDMA,WLAN(802.11a/b/g)).The implementation is achieved by a 0.13μm RF CMOS process.The measured results demonstrate that three quadrature VCOs(QVCO) continuously cover the frequency from 3.1 to 6.1 GHz(65.2%),and through the successive divide-by-2 prescalers to achieve the frequency from 0.75 to 6.1 GHz continuously.The chip was fully integrated with the exception of an off-chip filter.The entire chip area is only 3.78 mm~2,and the system consumes a 21.7 mA@1.2 V supply without output buffers.The lock-in time of the PLL frequency synthesizer is less than 4μs over the entire frequency range with a direct frequency presetting technique and the auxiliary non-volatile memory(NVM)can store the digital configuration signal of the system,including presetting signals to avoid the calibration process case by case.     

A 0.13μm CMOS △∑ fractional-N frequency synthesizer for WLAN transceivers

A fractional-N frequency synthesizer fabricated in a 0.13 μm CMOS technology is presented for the application of IEEE 802.11 b/g wireless local area network (WLAN) transceivers.A monolithic LC voltage controlled oscillator (VCO) is implemented with an on-chip symmetric inductor.The fractional-N frequency divider consists of a pulse swallow frequency divider and a 3rd-order multistage noise shaping (MASH) △ ∑ modulator with noise-shaped dithering techniques.Measurement results show that in all channels,phase noise of the synthesizer achieves -93 dBc/Hz and -118 dBc/Hz in band and out of band respectively with a phase-frequency detector (PFD) frequency of 20 MHz and a loop bandwidth of 100 kHz.The integrated RMS phase error is no more than 0.8°.The proposed synthesizer consumes 8.4 mW from a 1.2 V supply and occupies an area of 0.86 mm2.     

LC voltage controlled oscillator in 0.18-μm RF CMOS

An integrated low-phase-noise voltage-controlled oscillator(VCO) has been designed and fabricated in SMIC 0.18μm RF CMOS technology.The circuit employs an optimally designed LC resonator and a differential cross-coupling amplifier acts as a negative resistor to compensate the energy loss of the resonator.To extend the frequency tuning range,a three-bit binary-weighted switched capacitor array is used in the circuit.The testing result indicates that the VCO achieves a tuning range of 60%from 1.92 to 3.35 GHz.The phase noise of the VCO is -117.8 dBc/Hz at 1 MHz offset from the carrier frequency of 2.4 GHz.It draws 5.6 mA current from a 1.8 V supply.The VCO integrated circuit occupies a die area of 600×900μm~2.It can be used in the IEEE802.11 b based wireless local network receiver.     

A monolithic 3.1-4.8 GHz MB-OFDM UWB transceiver in 0.18-μm CMOS

正A monolithic RF transceiver for an MB-OFDM UWB system in 3.1-4.8 GHz is presented.The transceiver adopts direct-conversion architecture and integrates all building blocks including a gain controllable wideband LNA,a I/Q merged quadrature mixer,a fifth-order Gm-C bi-quad Chebyshev LPF/VGA,a fast-settling frequency synthesizer with a poly-phase filter,a linear broadband up-conversion quadrature modulator,an active D2S converter and a variablegain power amplifier.The ESD protected transceiver is fabricated in Jazz Semiconductor's 0.18-μm RF CMOS with an area of 6.1 mm~2 and draws a total current of 221 mAfrom 1.8-V supply.The receiver achieves a maximum voltage gain of 68 dB with a control range of 42 dB in 6 dB/step,noise figures of 5.5-8.8 dB for three sub-bands,and an inband /out-band IIP_3 better than-4 dBm/+9 dBm.The transmitter achieves an output power ranging from-10.7 to-3 dBm with gain control,an output P_(1dB) better than-7.7 dBm,a sideband rejection about 32.4 dBc,and LO suppression of 31.1 dBc.The hopping time among sub-bands is less than 2.05 ns.     

A 6.25 Gb/s equalizer in 0.18μm CMOS technology for high-speed SerDes

This paper presents a 0.18μm CMOS 6.25 Gb/s equalizer for high speed backplane communication. The proposed equalizer is a combined one consisting of a one-tap feed-forward equalizer （FFE） and a two-tap half-rate decision feedback equalizer （DFE） in order to cancel both pre-cursor and post-cursor ISI. By employing an active-inductive peaking circuit for the delay line, the bandwidth of the FFE is increased and the area cost is minimized. CML-based circuits such as DFFs, summers and multiplexes all help to improve the speed of DFEs. Measurement results illustrate that the equalizer operates well when equalizing 6.25 Gb/s data is passed over a 30-inch channel with a loss of 22 dB and consumes 55.8 mW with the supply voltage of 1.8 V. The overall chip area including pads is 0.3 × 0.5 mm^2.     

A 5-GHz programmable frequency divider in 0.18-μm CMOS technology

正A 5-GHz CMOS programmable frequency divider whose modulus can be varied from 2403 to 2480 for 2.4-GHz ZigBee applications is presented.The divider based on a dual-modulus prescaler(DMP) and pulse-swallow counter is designed to reduce power consumption and chip area.Implemented in the 0.18-μm mixed-signal CMOS process,the divider operates over a wide range of 1-7.4 GHz with an input signal of 7.5 dBm;the programmable divider output phase noise is -125.3 dBc/Hz at an offset of 100 kHz.The core circuit without test buffer consumes 4.3 mA current from a 1.8 V power supply and occupies a chip area of approximately 0.015 mm~2.The experimental results indicate that the programmable divider works well for its application in frequency synthesizers.     

A monolithic 3.1-4.8 GHz MB-OFDM UWB transceiver in 0.18-μm CMOS

A monolithic RF transceiver for an MB-OFDM UWB system in 3.1-4.8 GHz is presented.The transceiver adopts direct-conversion architecture and integrates all building blocks including a gain controllable wideband LNA,a I/Q merged quadrature mixer,a fifth-order Gm-C bi-quad Chebyshev LPF/VGA,a fast-settling frequency synthesizer with a poly-phase filter,a linear broadband up-conversion quadrature modulator,an active D2S converter and a variablegain power amplifier.The ESD protected transceiver is fabricated in Jazz Semiconductor's 0.18-μm RF CMOS with an area of 6.1 mm2 and draws a total current of 221 mA from 1.8-V supply.The receiver achieves a maximum voltage gain of 68 dB with a control range of 42 dB in 6 dB/Step,noise figures of 5.5-8.8 dB for three sub-bands,and an inband/out-band IIP3 better than-4 dBm/+9 dBm.The transmitter achieves an output power ranging from-10.7 to-3dBm with gain control,an output P1dB better than-7.7 dBm,a sideband rejection about 32.4 dBc,and LO suppression of 31.1 dBc.The hopping time among sub-bands is less than 2.05 ns.     

A 7-GHz multiloop ring oscillator in 0.18-μm CMOS technology

A novel delay stage for ring oscillator utilizing multiloop technique is presented in this paper. Different conventional delay stages for the multiloop ring oscillators have been reviewed and analyzed in this work. By using push-pull inverter as the secondary input in its delay cell, the proposed oscillator demonstrates a frequency improvement of up to 17% when compared with conventional designs. The fabricated oscillator is measured to cover a frequency range of 6.24–7.04 GHz. Operating in 1.8-V power supply, the oscillator manifests itself a phase noise of ?107.7 dBc/Hz@10 MHz offset from a center frequency of 6.25 GHz. The proposed oscillator consumes a current of 40–51 mA from the 1.8-V supply and occupies an area of 440 μm ×  430 μm.     

A 5.25-GHz low-power down-conversion mixer in 0.18-μm CMOS technology

A 5.25 GHz low voltage, high linear and isolated mixer using TSMC 0.18 μm CMOS process for WLAN receiver was investigated. The paper presents a novel topology mixer that leads to better performance in terms of linearity, isolation and power consumption for low supply voltage. The measuring results of the proposed mixer achieve: 7.6 dB power conversion gain, 11.4 dB double side band noise figure, 3 dBm input third-order intercept point, and the total dc power consumption of this mixer including output buffers is 2.45 mW from a 1 V supply voltage. The current output buffer is about 2 mW, the excellent LO-RF, LO-IF and RF-IF isolation achieved up to 37.8, 54.8 and 38.2 dB, respectively.     

Design of a high-order single-loop Σ△ ADC followed by a decimator in 0.18μm CMOS technology

This work presents an oversampled high-order single-loop single-bit sigma–delta analog-to-digital converter followed by a multi-stage decimation filter.Design details and measurement results for the whole chip are presented for a TSMC 0.18μm CMOS implementation to achieve virtually ideal 16-b performance over a baseband of 640 kHz.The modulator in this work is a fully differential circuit that operates from a single 1.8 V power supply. With an oversampling ratio of 64 and a clock rate of 81.92 MHz,the modulator achieves a 94 dB dynamic range. The decimator achieves a pass-band ripple of less than 0.01 dB,a stop-band attenuation of 80 dB and a transition band from 640 to 740 kHz.The whole chip consumes only 56 mW for a 1.28 MHz output rate and occupies a die area of 1×2 mm^2.     

A 5 Gb/s transceiver in 0.13μm CMOS for PCIE2.0

This paper presents a CML transceiver for a PCI-express generation 2 physical layer protocol that has been fabricated by SMIC’s 0.13μm CMOS technology.The active area of the transceiver is 0.016 mm~2 and it consumes a total of 150 mW power at a 1.2 V supply voltage.The transmitter uses two stage pre-emphasis circuits with active inductors,reducing inter-symbol interference and extended bandwidth;the receiver uses a time-domain adaptive equalizer,the circuit uses an inductive peaking technique and extends the bandwidth,and the use of active inductors reduces the circuit area and power consumption effectively.The measurement results show that this circuit could stably transmit the signal at the data rate of 5 Gbps,the output signal swing of the transmitter is 350 mV with jitter of 14 ps,the eye opening of the receiver is 135 mV and the eye width is 0.56 UI.The circuit performance sufficiently meets the requirements of the PCI-Express 2.0 protocol.     

A 1.0 V differential VCO in 0.13 μm CMOS technology

A differential complementary LC voltage controlled oscillator(VCO) with high Q on-chip inductor is presented.The parallel resonator of the VCO consists of inversion-mode MOS(I-MOS) capacitors and an on-chip inductor.The resonator Q factor is mainly limited by the on-chip inductor.It is optimized by designing a single turn inductor that has a simulated Q factor of about 35 at 6 GHz.The proposed VCO is implemented in the SMIC 0.13μm 1P8M MMRF CMOS process,and the chip area is 1.0×0.8 mm~2.The free-running frequency is from 5.73 to 6.35 GHz.When oscillating at 6.35 GHz,the current consumption is 2.55 mA from a supply voltage of 1.0 V and the measured phase noise at 1 MHz offset is -120.14 dBc/Hz.The figure of merit of the proposed VCO is -192.13 dBc/Hz.     

A 4224 MHz low jitter phase-locked loop in 0.13-μm CMOS technology

A 4224 MHz phase-locked loop(PLL) is implemented in 0.13μm CMOS technology.A dynamic phase frequency detector is employed to shorten the delay reset time so as to minimize the noise introduced by the charge pump.Dynamic mismatch of charge pump is considered.By balancing the switch signals of the charge pump,a good dynamic matching characteristic is achieved.A high-speed digital frequency divider with balanced input load is also designed to improve in-band phase noise performance.The 4224 MHz PLL achieves...     

A 4224 MHz low jitter phase-locked loop in 0.13-μm CMOS technology

A 4224 MHz phase-locked loop (PLL) is implemented in 0.13 μm CMOS technology. A dynamic phase frequency detector is employed to shorten the delay reset time so as to minimize the noise introduced by the charge pump. Dynamic mismatch of charge pump is considered. By balancing the switch signals of the charge pump, a good dynamic matching characteristic is achieved. A high-speed digital frequency divider with balanced input load is also designed to improve in-band phase noise performance. The 4224 MHz PLL achieves phase noises of-94 dBc/Hz and -114.4 dBc/Hz at frequency offsets of 10 kHz and 1 MHz, respectively. The integrated RMS jitter of the PLL is 0.57 ps (100 Hz to 100 MHz) and the PLL has a reference spur of-63 dB with the second order passive low pass filter.     

A 3-5 GHz TH-UWB transmitter in 0.18-μm RF CMOS technology

5 mV at a 50 Ω load from a 1.8-V supply, the return loss (S11) at the output port is less than -10 dB, and the chip size is 0.7 × 0.8 mm2, with a power consumption of 12.3 mW.