基于量子遗传算法的嵌入式系统软硬件划分算法

针对嵌入式系统软硬件协同设计中的软硬件划分问题，本文在改进了基于基本调度块图的软硬件划分模型的基础上，提出了一个基于量子遗传算法(QGA)的软硬件划分算法。通过采用自适应的适应度函数、惯性量子旋转角调整策略以及引入量子交叉操作，提高了算法的搜索效率，实验结果说明了该算法对解决软硬件划分问题的有效性。     

高效关键路径粒子群的软硬件划分算法

软硬件划分是在满足系统约束条件下,将系统中部分功能模块由硬件实现,部分功能模块由软件实现,使系统整体性能达到最优.本文采用有向无环图对划分问题建模,提出采用关键路径调度、自适应性的高效粒子群软硬件划分算法.实验结果表明,采用本文算法,所得结果明显优于采用先来先服务的调度方法.     

一种基于FPGA的自适应遗传算法

采用了一种适合硬件实现的自适应遗传算法,利用种群的最大适应度fmax﹑最小适应度fmin和适应度平均值fave这3个变量来自适应地控制整个种群的交叉概率pc 和变异概率pm 。选用了适合硬件实现的选择﹑交叉﹑变异算子,并将它们设计成流水线结构, 同时,将选择算子与适应度计算并行化,大大提高了算法的运行效率。整个设计采用了XILINX公司的XC2V1000型号的FPGA芯片。算法利用VHDL语言来描述。实现后的测试表明,这种自适应遗传算法明显改善了算法的搜索性能和全局收敛性,同时利用硬件实现有效减少了运行时间,使其在一些实时性要求较高的场合得到应用成为可能。     

基于扩展背包问题的的软硬件划分算法

软硬件划分问题常以时间为约束对硬件面积进行优化。随着嵌入式的发展，功耗这一因素也越来越重要，故在约束条件中加入了功耗的约束。贪婪算法是解决0-1背包问题的一种简单有效的方法，因此建立多约束的软硬件划分问题与0-1背包问题之间的联系，采用扩展的贪婪算法解决多性能指标的软硬件划分问题。利用仿真与动态规划方法的对比，进行了有效性验证。     

改进多路软硬件划分算法的筛选法

文章提出筛选法对基于抽象体系结构模板的多路软硬件划分算法进行了改进,从而使整个软硬件划分-任务调度过程的时间大大缩短。该方法在原算法的软硬件划分和任务调度过程之间加入了一个筛选步骤,对软硬件划分结果的硬件面积进行预估,依据预估的结果进行筛选,筛选后满足要求的划分方案才进行调度,从而大大减少了调度过程的工作量。实验结果表明,加入筛选步骤后,在最终结果性能基本不损失的前提下,整个软硬件划分-任务调度过程的速度有明显提高。     

一种基于排序操作的进化算子自适应遗传算法

提出了一咱基于排序操作的进化算子自适应的遗传算法,该算法中,每个体按适应值大小进行排序,个体的选择、交叉、交异算子的概率根据个体排序值来自适应地确定,其中选择概率还随进化过程而调节,利用Ｍａｒｋｏｖ链的分析法证明了该算法的全局收敛性,最后,实验结果表明该算法同传统的遗传算法相比不仅能收敛到全局最优解,而且具有交快的收敛速度。     

一种基于SystemC的软硬件协同设计方法

随着集成电路工艺的飞速发展,传统的设计方法已不能满足设计高集成度的复杂数字系统的要求。软硬件协同设计成为嵌入式系统设计的新方法。SystemC是一种兼容C++的系统建模语言,它同时支持RTL级、行为级和系统级描述,使其成为软硬件协同设计平台的基础。     

面向OFDM接收机的一种自适应自动增益控制策略

 针对大动态范围、高峰均比的OFDM信号,提出了一种新的自适应自动增益控制(AGC)策略.本策略采用具有混合增益补偿系数的平均绝对误差自动增益控制结构,并增加了可编程的绝对能量误差参考门限,实现了灵活的多步长增益补偿机制.同时,考虑到低功耗设计的要求,AGC电路可以给出增益调整成功标志信号.此外,该算法具有良好的可扩展性.     

一种自适应遗传算法及其应用

遗传算法的性能深受算法参数的影响.为提高算法的搜索性能,避免算法在寻优搜索中陷入局部极值,将一种新的自适应遗传算法用于函数优化中,对三个常用的标准测试函数进行了优化,并将其用于立体图像对的匹配中.通过实验与简单遗传算法进行比较,表明该算法提高了搜索性能.     

一种基于自适应遗传算法的BP网络的应用

针对遗传算法和BP网络各自的优缺点，探讨了两算法结合的必要性、可能性以及结合方法，提出了一种改进的自适应遗传算法，并把该算法用于优化BP网络的权值。把经优化后的BP网络作为汉字识别的分类器，实验结果验证了所述方法的有效性。     

An Iterative Algorithm for Hardware-Software Partitioning, Hardware Design Space Exploration and Scheduling

The paper proposes a novel heuristic technique for integrated hardware-software partitioning, hardware design space exploration and scheduling. The technique maps an application specified as a task graph on a heterogeneous architecture with an objective to minimize the latency of the task graph subject to the area constraint on the hardware coprocessor. The technique uses an iterative approach where the partitioner decides the processor mapping and HW design points of some tasks. The scheduler then simultaneously decides the processor mapping, HW design point and schedule time of the remaining tasks. There exists a tight coupling between the two design stages allowing them to produce superior quality designs in fewer iterations. The technique accounts for the time overheads due to inter-processor /intra-processor communication and shared memory access conflicts. It can therefore be used for both communication intensive and computation intensive applications. The technique also considers dynamic reconfiguration capability of the hardware coprocessor. The technique performs tradeoff analysis and maps hardware tasks to mutually exclusive temporal segments if this results in lower latency. The effectiveness of the technique is demonstrated by a case study of the JPEG image compression algorithm, comparison with an optimal ILP based approach and experimentation with synthetic graphs.     

Comparing Three Heuristic Search Methods for Functional Partitioning in Hardware–Software Codesign

This paper compares three heuristic search algorithms: genetic algorithm (GA), simulated annealing (SA) and tabu search (TS), for hardware–software partitioning. The algorithms operate on functional blocks for designs represented as directed acyclic graphs, with the objective of minimising processing time under various hardware area constraints. Thecomparison involves a model for calculating processing time based on a non-increasing first-fit algorithm to schedule tasks, given that shared resource conflicts do not occur. The results show that TS is superior to SA and GA in terms of both search time and quality of solutions. In addition, we have implemented an intensification strategy in TS called penalty reward, which can further improve the quality of results.     

一种基于改进模拟退火算法的软硬件划分技术

提出一种应用于嵌入式系统软硬件划分的改进模拟退火算法.算法通过使用基于Cauchy分布的扰动模型和Tsallis接收准则来提高模拟退火算法的性能.通过对比经典的模拟退火软硬件划分技术以及实验结果的验证表明,使用改进模拟退火算法能加快划分的收敛,并且找到目标函数的最优值的概率也更大.     

Virtual Prototyping For Modular And Flexible Hardware-Software Systems

The goal of this work is to develop a methodology for fast prototyping of highly modular and flexible electronic systems including both, software and hardware. The main contribution of this work is the ability to handle a wide range of architectures. We assume that hardware/software partitioning is already made. This stage of the codesign process starts with a virtual prototype, an heterogeneous architecture composed of a set of distributed modules, represented in VHDL for hardware elements and in C for software elements, communicating through communication modules. This work concentrates on a modelling strategy that allow virtual prototype to be used for both cosynthesis (mapping hardware and software modules onto an architectural platform) and cosimulation (that is the joint simulation of hardware and software components) into an unified environment. The main contribution is the use of a multi-view library concept in order to hide specific hardware/software implementation details and communication schemes. In particular this approach addresses the problem of communication between the hardware and software modules.     

An Algorithm for Hardware/Software Partitioning Using Mixed Integer Linear Programming

One of the key problems in hardware/software codesign is hardware/software partitioning. This paper describes a new approach to hardware/software partitioning using integer programming (IP). The advantage of using IP is that optimal results are calculated for a chosen objective function. The partitioning approach works fully automatic and supports multi-processor systems, interfacing and hardware sharing. In contrast to other approaches where special estimators are used, we use compilation and synthesis tools for cost estimation. The increased time for calculating values for the cost metrics is compensated by an improved quality of the values. Therefore, fewer iteration steps for partitioning are needed. The paper presents an algorithm using integer programming for solving the hardware/software partitioning problem leading to promising results.     

Hardware-Software Partitioning for Real-Time Embedded Systems

In this paper, we present an approach to hardware-software partitioning for real-time embedded systems. Hardware and software components are modeled at the system level, so that cost and performance tradeoffs can be studied early in the design process and a large design space can be explored. Feasibility factor is introduced to measure the possibility of a real-time system being feasible, and is used as both a constraint and an attribute during the optimization process. An imprecise value function is employed to model the tradeoffs among multiple performance attributes. Optimal partitioning is achieved through the use of an existing computer-aided design tool. We demonstrate the application of our approach through the design of an example embedded system.     

VLSI电路划分问题的分散搜索算法

电路划分是超大规模集成电路(VLSI)设计自动化中的一个关键阶段,是NP困难的组合优化问题.本文把基于顶点移动的Fiduccia-Mattheyses(FM)算法结合到分散搜索算法框架中,提出了电路划分的分散搜索算法.算法利用FM算法进行局部搜索,利用分散搜索的策略进行全局搜索.为满足该方法对初始解的质量和多样性的要求,采用贪心随机自适应搜索过程(GRASP)和聚类相结合的方法产生初始解.实验结果表明,算法可以求解较大规模的电路划分实例,且与基于多级框架的划分算法hMetis相比,划分的质量有明显的提高.