基于Booth\CSD混合编码的模 乘法器的设计

在余数系统的设计中,模加法器和模乘法器的设计处于核心地位,尤其是模乘法器的性能,是衡量余数系统系能的主要标志之一。文中先推导出Booth编码下的模 乘法器设计的算法,然后针对Booth编码模乘法器设计中译码电路复杂的问题,提出了一种基于Booth/ CSD混合编码的模乘法器设计方法,基于Booth/CSD编码的模乘法器部分积的位宽相对传统的Booth编码乘法器而言,减少了50%;经试验证明,与传统的基-Booth编码的模乘法器相比这种混合编码的模乘法器的速度提高了5%,面积减少24.7%。     

基于Booth\CSD混合编码的模2~n+1乘法器的设计

在余数系统的设计中,模加法器和模乘法器的设计处于核心地位,尤其是模乘法器的性能,是衡量余数系统系能的主要标志之一。文中先推导出Booth编码下的模2n+1乘法器设计的算法,然后针对Booth编码模乘法器设计中译码电路复杂的问题,提出了一种基于Booth/CSD混合编码的模乘法器设计方法,基于Booth/CSD编码的模乘法器部分积的位宽相对传统的Booth编码乘法器而言,减少了50%;经试验证明,与传统的基-Booth编码的模乘法器相比这种混合编码的模乘法器的速度提高了5%,面积减少24.7%。     

32位嵌入式定/浮点乘法器设计

文章提出一种RISC MCU中的32位嵌入式定／浮点乘法器的设计，用于完成32位定／浮点乘除法。利用一种新的改进型三阶Booth算法，并采取Wallace树结构及CSA加法器，与基于二阶Booth算法的设计相比，该乘法器运算速度提高了1／3以上。     

一种结构新颖的流水线Booth乘法器设计

在对传统Booth乘法器研究的基础上,介绍了一种结构新颖的流水线型布什(Booth)乘法器。使用基-4 Booth编码、华莱士树(Wallace Tree)压缩结构、64位Kogge-Stone前缀加法器实现,并在分段实现的64位Kogge-Stone前缀加法器中插入4级流水线寄存器,实现32 t×32 bit无符号和有符号数快速乘法。用硬件描述语言设计该乘法器,使用现场可编程门阵列(Field Programmable Gate Array,FPGA)进行验证,并采用SMIC 0.18 μm CMOS标准单元工艺对该乘法器进行综合。综合结果表明,电路的关键路径延时为3.6 ns,芯片面积＜0.134 mm,功耗＜32.69 mW。     

基于FPGA的数字乘法器性能比较

详细描述了四种基本的FPGA数字乘法器设计方法即阵列法、查找表法、移位相加法、Booth法的原理和实现过程.以4×4和16×16数字乘法器的设计为例,通过在AlteraFPGA芯片上的仿真与综合,给出了这四种数字乘法器的运算速度和占用逻辑资源情况.结果表明随着位宽的变化,各方法的相对效果会有变化,对于具有较宽数据位的乘...     

基于16位定点DSP的并行乘法器的设计

设计了一种用于1 6位定点DSP中的片内乘法器.该乘法器采用了改进型Booth算法,使用CSA构成的乘法器阵列,并采用跳跃进位加法器实现进位传递,该设计具有可扩展性,并提出了更高位扩展时应改进型方向.设计时综合考虑了高性能定点DSP对乘法器在面积和速度上的要求,具有极其规整的布局布线.     

一种改进的基4-Booth编码流水线大数乘法器设计

大数乘法器是密码算法芯片的引擎,它直接决定着密码芯片的性能.由此提出了一种改进的基4-Booth编码方法来缩短Booth编码的延时,并提出了一种三级流水线大数乘法器结构来完成256位大数乘法器的设计.基于SMIC0.18μm工艺,对乘法器设计进行了综合,乘法器的关键路径延时3.77ns,它优于同类乘法器.     

一种高压缩Wallace树的快速乘法器设计

介绍了一种32位有符号/无符号乘法器.该乘法器采用改进的Booth编码减少了部分积个数,并通过符号扩展的优化,减少中间资源消耗,对部分积进行统一的符号操作,简化了程序设计的复杂性.采用了7:2压缩结构的Wallace树及64位Brent Kung树结构超前进位加法器,有效地提高了乘法器计算速度.整个设计采用Verilog语言编写,通过Modelsim仿真验证设计功能的正确性.采用Synopsys的Design Compiler进行基于SMIC的0.18微米标准库的综合并得到性能参数.     

32位RISC处理器中可配置乘法器的设计

“ENOD”是某公司2006年设计的一款32位嵌入式RISC微处理器。其中的硬件乘法器位于设计的关键时序路径上，为优化乘法器的时序和提高其灵活性，采用Radix4-Booth算法，设计了单周期、流水线和多周期3种乘法器结构，在Modelsim中进行了功能仿真和时序仿真。采用中芯国际0．18μm的标准单元库将它们分别在DC中综合后，从功能、面积、速度等方面对这3种乘法器结构做了定量分析，指出了它们各自的优缺点及应用场合。在“ENOD”的应用中，根据具体的应用通过设置参数选择最合适的乘法器结构，灵活性好，性能/面积比高。     

优化FIR数字滤波器的FPGA实现

基于提高速度和减少面积的理念,对传统的FIR数字滤波器进行改良。考虑到FPGA的实现特点,研究并设计了采用Radix2的Booth算法乘法器以及结合了CSA加法器和树型结构的快速加法器,并成功应用于FIR数字滤波器的设计中。滤波器的系数由Matlab设计产生。仿真和综合结果表明,Booth算法乘法器和CSA算法加法器树,在满足FIR数字滤波器的性能要求的同时,在电路实现面积上、尤其是速度上有明显的优化;并且当数据量越多时,优化也越明显。     

A high yield buried p-layer fabrication process for GaAs LSIcircuits

GaAs MESFETs for LSI and VLSI require high transconductance to drive large wiring loads, but they must also exhibit extremely good uniformity and reproducibility. To provide ion-implanted MESFETs that meet these conflicting needs, the authors developed a 0.7-μm buried p-layer (BP) multifunction self-aligned gate (MSAG) fabrication process which has demonstrated excellent yields for circuits of up to 5000 gates. Device and circuit performance has been studied as a function of BP implant dose. LSI circuit yield and performance have been characterized using 4×4-, 8×8-, 12×12-, 16×16-, and 20×20-bit parallel-array multipliers on the same die. A high-dose BP implant has resulted in σV_T as low as 8 mV over 3-in wafers and 20×20-bit multipliers with self-test yields of 61%. Measured worst-case multiplication times range from 870 ps for the 4×4-bit to 6.5 ns for the 20×20-bit multipliers, representing record speeds for these multipliers. The average gate delays for these multipliers are 51 to 67 ps, the fastest extracted gate delays reported for LSI circuits     

一种8位单片机中ALU的改进设计

文章提出了一种精简指令集8位单片机中，算术逻辑单元的工作原理。在此基础上，对比传统PIC方案、以及在ALU内部再次采用流水线作业的332方案、44方案，并用Synopsys综合工具实现了它们。综合及仿真结果表明。根据该单片机系统要求，44方案速度最高，比332方案可提高43．9％，而面积仅比最小的332方案增加1．6％。在分析性能差异的根本原因之后，阐明了该方案的优越性。     

Design and Implementation of 160×192 Pixel Array Capacitive-Type Fingerprint Sensor

The application specific integrated circuit implementation of a capacitive fingerprint sensor system-on-chip (SOC), which embeds a 32-bit microcontroller for performing an identification algorithm, is described for user authentication on small, thin, and portable equipment. The SOC is composed of 160 × 192 array cells with a sensor detection circuit and an embedded 32-bit reduced instruction set computer (RISC) microcontroller. The proposed sensor detection circuit increases the voltage difference between a ridge and valley about 80% more than conventional circuits and minimizes an electrostatic discharge influence by applying an effective isolation structure. The 32-bit RISC microcontroller is embedded by a latch base for low power and low complexity. The test chip was fabricated on a 0.35 μm standard complementary metal oxide semiconductor 1-poly 4-metal process.     

High Performance Modified Static Segment Approximate Multiplier based on Significance Probability

Achieving high accuracy has become a key design objective in high quantity digital data computing devices. To enhance the accuracy, a high performance Modified Static Segment approximate Multiplier (MSSM) is proposed in this paper. It increases the accuracy based on the negating lower order significant information of input operands using Significance Estimator Logic Circuit (SELC). The performance of proposed MSSM is compared with the existing approximate multipliers such as a Dynamic Segment approximate Multiplier (DSM) and Static Segment approximate Multiplier (SSM) for all input combinations. These multipliers are implemented and simulated using Xilinx 14.2 ISE. In MSSM method, 99% of average computational accuracy can be achieved for a 16-bit multiplication even with an 8?×?8-bit multiplier from all combinations of input operands instead of 95% of average computational accuracy from 61% of input operand pair in the existing SSM method. The proposed 16-bit MSSM offers a savings of 83.45% LUTs, 38.78% power and it exhibits 24.40% less delay, 0.6% less computational accuracy than the existing DSM.     

8位RISC MCU IP核的设计

本文介绍了一种嵌入式RISCMCUIP核的具体设计。该核采用哈佛结构,单周期单指令,指令集与PIC16C57兼容,并且具有低功耗特性和LCD驱动能力。     

32位RISC微处理器设计

介绍了一种与Motorola-Mcore兼容的32位RISC结构微处理器核的设计。从该处理器的整体结构的划分，到处理器内部各单元的设计，进行了比较详尽的阐述，最后给出了设计的综合结果，并对该设计进行了软件仿真和硬件验证。     

Single-chip microcomputer control of the inverter by the magneticflux control PWM method [machine control]

Single-chip microcomputer control of a pulsewidth-modulated (PWM) inverter for motor drive applications is presented. The PWM pattern generation and the system control of the inverter are achieved by software of the 8-bit single-chip microcomputer. The single-chip microcomputer has a low processing speed and small memory capacity, disadvantages that can be overcome by the magnetic flux control PWM method. The PWM pattern is generated every 90 μs. The memory capacity of the PWM look-up table is less than 2 kbytes. Experimental results show that the motor performances are the same as that of the multichip triangular-sinewave PWM inverter     

A single chip radix-2 FFT butterfly architecture using parallel data distributed arithmetic

It is shown how distributed arithmetic techniques can be applied in parallel-data arithmetic computations to achieve highly regular and efficient VLSI structures on silicon. Two individual arithmetic processor chips are described as examples of the technique. The chips described, which are intended primarily for computation of the FFT butterfly, each contain the functional equivalence of two parallel pipelined multipliers. The first chip is an 8-bit prototype device which has been designed and fabricated on a standard 5-/spl mu/m silicon-gate n-channel MOS process. The second chip is a 16-bit CMOS-SOS design which uses a modified architecture to achieve higher clocking rates and improved versatility in systems use.     

32位定/浮点乘法器设计

针对Wallace树连接线复杂度高,版图实现比较困难的缺点,提出了一种新的加法器阵列结构.这种结构在规则性和连接复杂度方面优于ZM树和OS树.同时提出一种新的CLA加法器结构以提高乘法器的性能.乘法器采用1.5μm CMOS工艺实现,完成一次定点与浮点乘法操作的时间分别是56ns和76ns.