RFIC芯片的测试与设计验证

射频芯片(RFIC)的性能极易受到键合线、外围元件与电路等片外因素的影响,通常一款商用射频芯片的设计需要经过从初始芯片设计、芯片测试验证、修正芯片设计的多轮反复过程。因此射频芯片在设计时就需要对IC电路、键合和片外元件电路进行综合考虑。根据这一特点,结合相关芯片的实践经验,讨论射频芯片测试与验证的一般方法和经验技巧,对RFIC的设计具有实用价值。     

Au线键合中"塌线"问题的研究

目前,在半导体闪存多芯片的金线键合工艺中,为满足堆叠芯片不断增加等结构需要,键合线弧要求更低、更长,制造工艺变得相对更加复杂。针对生产过程中常遇到的塌线问题,通过对金线键合工艺中线弧形成动作的过程分析,以金线弹动现象为线索,探究了生产过程中塌线问题产生的原因,并给出了相应解决方案。经过此研究,长线键合的生产工艺能力得到加强,其成果对新封装产品的研发及基板设计具有有益的参考价值。     

一种基于基片集成波导技术的引线键合结构

当前微波毫米波芯片的引线键合主要是在芯片焊盘和微带线之间实施,当工作频率达到毫米波频段,引线键合的性能对键合线属性及微带线加工精度的敏感度越来越高,键合操作中键合线长度的差异或微带线加工的误差都可能导致键合性能的快速恶化。文章提出了一种基于基片集成波导(SIW)的引线键合结构,该结构直接使用SIW与芯片焊盘或其他电路进行键合,对比现有微带键合方案,使用本文提出的基于SIW的键合方案,可以显著减小加工精度的敏感度,同时减少对介质基片的限制等。文章分别设计了无源和有源SIW键合结构,仿真和测试结果表明:基于SIW的键合结构拥有良好的键合性能,相比微带键合结构,降低了传输损耗、降低了对结构尺寸的灵敏度、改善了键合性能。     

键合线互连电路的优化设计

介绍了一种微波多芯片组件中芯片与传输线互连的键合线互连电路设计。采用低通滤波器方法设计的键合线互连电路结构,在键合线长度一定的情况下,能够显著提高键合线互连电路的频率响应。设计了一种基于3阶低通滤波器的键合线互连电路,将键合线的寄生电感融入了3阶低通滤波器中,改善了键合线互连电路的微波传输特性,提高了键合线互连电路的截止频率。采用微波电路设计软件和三维电磁场软件相结合的设计方法,对键合线互连电路的微波特性进行建模、分析,验证了这种电路设计方法的正确性。     

键合线弧高度对键合拉力的影响分析

在集成电路封装的质量控制中,键合拉力的地位非常重要。作为键合质量好坏的主要判定基准之一,影响键合拉力的因素有很多,包括键合工艺参数、焊线材料类型、拉力测试吊钩的测试位置、焊线线径以及线弧的长度和高度等。主要讨论在键合线弧投影长度不变的情况下,线弧高度的变化对键合拉力产生的影响。通过对不同线弧高度条件下测得的拉力数据进行整理分析,结果表明:键合线弧越高,拉力就越大;反之,拉力则越小。这为集成电路组装的正常量产过程中,工程技术人员对于键合线弧整体高度的合理有效控制及键合拉力规范的合理定义提供了参考依据。     

中芯国际与安捷伦科技合作建立RFIC测试联合实验室

全球最大的芯片代工厂之一-中芯国际集成电路制造有限公司与全球最大的测试测量公司安捷伦科技共同宣布合作建立“中芯国际-安捷伦科技RFIC联合实验室”，旨在为中国的无线通信射频集成电路及其模块和移动通讯终端产品的研发、设计、流片、测试提供强有力的技术保障。该实验室的建立有助于提高RFIC设计公司的设计能力，缩短设计流片周期，提高芯片的一次性成功率，确保RFIC公司的产品可以尽快成功上市。[第一段]     

微系统感应局部加热封装与键合设计

整体加热封装(即封装过程中整个衬底、芯片、键合层都处于加热状态),不仅工艺时间长,而且高温会对衬底上温度敏感的微结构和电路产生热损坏,或者因为热膨胀系数不匹配导致键合区热应力增大,影响器件可靠性。首先对电磁感应加热实现微系统局部加热封装进行了论述,重点对感应局部加热键合原理、电源选择、感应器和键合层设计,以及键合过程中的温度测试等方面进行了设计分析。对于感应局部加热键合而言,键合区必须设计成封闭环形,其宽度应大于临界尺寸,并且存在一个最佳频率范围。根据键合层材料和结构不同,感应局部加热可用于焊料键合、共晶键合、扩散键合,以实现微系统器件的封装和结构制作。     

含TSV结构的3D封装多层堆叠Cu/Sn键合技术

研究了利用Cu/Sn对含硅通孔(TSV)结构的多层芯片堆叠键合技术。采用刻蚀和电镀等工艺,制备出含TSV结构的待键合芯片,采用扫描电子显微镜(SEM)对TSV形貌和填充效果进行了分析。研究了Cu/Sn低温键合机理,对其工艺进行了优化,得到键合温度280℃、键合时间30 s、退火温度260℃和退火时间10 min的最佳工艺条件。最后重点分析了多层堆叠Cu/Sn键合技术,采用能谱仪(EDS)分析确定键合层中Cu和Sn的原子数比例。研究了Cu层和Sn层厚度对堆叠键合过程的影响,获得了10层芯片堆叠键合样品。采用拉力测试仪和四探针法分别测试了键合样品的力学和电学性能,同时进行了高温测试和高温高湿测试,结果表明键合质量满足含TSV结构的三维封装要求。     

功率元器件互连 从线键合到区域焊接

本文有比较地研究了线键合和区域焊接两种功率芯片互连技术的生产过程、电 性能、热处理和可靠性,指出了功率芯片互连技术中线键合和区域焊接技术的优点和缺点。     

面向射频微系统应用的圆片-芯片集成工艺技术研究

利用Au-Sn共晶合金反应实现硅基圆片-芯片(Die to Wafer)键合是一种可行的集成方案,通过优化关键实验条件改善圆片-芯片键合层质量及键合强度,探索出适合射频微系统应用的D2W集成工艺条件;使用扫描电子显微镜(SEM)观察各组圆片-芯片界面质量状态,分析其键合层元素组成;在常温及300℃高温下完成水平推力测试,分析了键合样片键合强度和耐高温水平。结果表明:键合压力、Sn浸润时间、Au-Sn共晶合金温度及时间、芯片键合前处理等条件对键合层质量影响较大;对芯片进行前处理,使用少量助焊剂,240℃浸润2 min,并在温度为290℃、压力为4 N的条件下键合6 min,可以得到具备良好键合层质量的键合样片,水平推力达到55 N。     

A Rigorous Study of Package and PCB Effects on W-CDMA Upconverter RFICs

A Volterra-series analysis is presented to study the package and printed circuit board (PCB) effects on the linearity of two wideband code-division multiple-access upconverter RF integrated circuit (RFIC) designs. The first design adopts a recently popular micromixer with a class AB input stage. The second design is based on a commonly used Gilbert mixer with emitter degeneration. Both upconverter RFICs are designed to have the same adjacent channel power ratio (ACPR) in the chip-level simulation. After fabrication, packaging, and testing on the PCB, the micromixer-based design consumes less direct current, but causes more degradation in the ACPR performance due to the influence of package and PCB when compared to the Gilbert mixer-based design. The theoretical analysis indicates that the micromixer-based upconverter RFIC is rather susceptible to the parasitic effects from the ground interconnect and, therefore, it needs a better package solution with a lower ground inductance for practical use. Comparison between theory and measurement shows good agreement in predicting the variations of conversion gain and ACPR due to the presence of the package and PCB.     

A Novel Test Strategy for Fine Pitch Wafer-Level Packaged Devices

This paper describes an innovative test strategy comprising a compliant elastomer mesh for testing fine pitch wafer-level package (WLP) devices. The test probe, hardware, and sample preparation processes are detailed. The components of the test hardware socket such as the SMA connectors, coplanar transmission lines on the PCB, via, off-chip interconnect, and elastomer mesh probe have been modeled. A complete system-level model, with off-chip interconnects on the WLP device pads, has been developed. The measurement and model demonstrate that the prototype test socket performs at 5 GHz with an insertion loss of about 3 dB. WLP device with Bed-of-Nail interconnects are characterized. Functional test features of the system are also addressed.     

基于片外信号源的SoC低成本测试解决方案

随着SoC芯片集成度和复杂度的不断提高,其测试变得越来越复杂,测试成本也越来越高,如何降低过高的测试成本也逐渐成为研究的热点。卫星数字电视信道接收芯片作为机顶盒关键芯片之一,对低成本测试的要求也越来越迫切。文章针对某卫星数字电视信道接收芯片,通过分析该芯片的内部模块功能,采用片外信号源方法设计该芯片的低成本测试方案,并在自动测试系统T6575上实现。实际生产结果表明,该方法能极大降低芯片测试成本。     

A multifunctional test chip for microelectronic packaging and its application on RF property measurements

This paper develops a multifunctional test chip for property extractions on packaging design. Components on this test chip include the diodes as the temperature sensors; the polysilicon units as the heaters; the piezoresistors as the stress sensors; and the pads as well as the related metal connector designs for the electrical parameter extractions. To save the sensor numbers and the connecting wires, sensors on the test chip surface were put according to structure symmetry. Since each packaging design has its individual size, components on the test chip surface were laid based on assembly of small unit cells, so that flexible test chip size can be obtained to fit the requirements from different packaging dimensions. The inductance and capacitance for the packaging leads were also extracted under microwave frequency operations, and a testing fixture was built to cooperate the Quad Flat Package (QFP) samples with the RF-RLC meter. The availability of the new measurement system designs was demonstrated from the testing data.     

一种用于电池供电的无线内视镜系统的片上集成的电源管理单元

介绍了一种应用于电池供电的无线内视镜系统的片上集成的电源管理单元.该电源管理单元使用标准的0.18μm CMOS工艺与基带处理芯片集成在一起.电源管理单元的集成减小了系统成本,方便了PCB的设计并缩小了系统的尺寸.通过比较得到了优化的电源结构方案,并描述了该方案中子模块电路的具体实现.整个电源管理单元只需5个片外小电容元件,其整体消耗的静态电流小于100μA.此外,该方案还采用数字校准的方法以克服工艺偏差对电路性能的影响.本文还描述了电路所达到的性能指标及相应的测试结果.     

基于T2000的RFIC低成本测试解决方案

随着通信技术的飞速发展，作为无线传输的核心——RFIC也快速成长，含盖射频，基带，A／D，D／A转换电路的单硅片RFIC将成为主流，与此同时RFIC厂商也将面临严峻的测试任务，如何高效，低成本的测试复杂的RFIC将是个挑战，为解决生产厂商的测试难题，ADVANTEST推出了基于开放式架构（OPENSTAR）ATE测试系统T2000的RF测试模块。     

Cost and performance tradeoff analysis in radio and mixed-signal system-on-package design

An optimal total solution for radio and mixed-signal system integration needs tradeoffs between different design options. Among various design metrics, cost and performance are probably the two most important factors for design decisions. In this paper, we review and analyze cost-performance tradeoffs of system-on-chip (SOC) versus system-on-package (SOP) solutions for radio and mixed-signal applications. A new design methodology, which quantitatively predicts performance and cost gains of SOP versus SOC, is presented. The performance model evaluates various mixed-signal isolation techniques between sensitive analog/RF circuits and noisy digital circuits in SOC or SOP. The cost analysis includes new factors such as extra chip area and additional process steps for mixed-signal isolation, seamless integration of "virtual components" or intellectual property (IP) modules, yield and technology compatibility for merging logic, memory and analog/RF circuits on a single chip, and extra costs for moving passives off chip. In addition to these, a complete and systematic analysis method for on-chip versus off-chip passives tradeoffs is presented. The analysis and modeling techniques explore tradeoffs between performance, cost, robustness, and yield when different on-chip or off-chip passives are used. It thus provides a complete picture of quantitative tradeoffs for using on-chip or off-chip passives. The design methodology and analysis techniques are then demonstrated through several design examples in wireless applications. It is clearly shown that for all complex and high performance mixed-signal systems, SOP is a lower cost solution than SOC. Finally, some design guidelines for SOC versus SOP and on-chip versus off-chip are concluded.     

开关型DC-DC控制芯片片上软启动电路设计

针对传统开关型DC-DC:控制芯片软启动电路需使用片外电容,且难以实现全片上集成的缺点,提出一种全数字方式实现的片上软启动电路,可实现软启动功能的全片上集成.集成了该电路的控制芯片具有启动平稳、对启动瞬间的电压过冲和电流浪涌具有良好抑制功能等特点.由于减少了芯片的引脚和省去了片外电容,还有利于缩小整机体积,降低系统设计...     

A low-cost test solution for wireless phone RFICs

This article describes an IBM approach for testing high-volume, complex RFICs at a fraction of the cost of the integrated circuit. This approach uses a personal computer, a fast benchtop dc parametric analyzer, and RF-to-analog circuits to test an RFIC during the manufacturing process. The described system and methodology are specifically designed for high-volume test, where test cost is extremely important; they are not recommended for lower-volume products (less than 1 million per month). This article describes the system architecture and discusses design, maintenance, and implementation considerations. The system is designed to reduce the cost of a complex RFIC manufacturing test to equal that of a discrete component, such as a resistor or capacitor. Given the relatively easy implementation and the drastic cost reduction associated with the test solution, this architecture establishes a new standard for the future of RF test. In fact, this architecture may result in the fastest RF tester currently available.