VHDL Implementation of the Fast Wavelet Transform

In this paper, a VHDL implementation of a decomposition unit based on Mallat's fast Wavelet Transform, which utilizes a two-channel subband coder, is described. The units were simulated, synthesized, and optimized using Mentor^? design tools. The final design was verified with VHDL test benches and Matlab image processing tools. Results of the decomposition for color images validate the design. Utilizing a clock frequency of 25 MHz, a time period of 45 ms was estimated for the decomposition process of a 640 × 480 color image, which makes it feasible for real time video compression. The size of the layout was found to be within 2.5 × 2.5 mm, which suggests a 40 pin-package tiny frame. Paul Salama received the B.Sc. in Electrical Engineering (First Class Honors) from the University of Khartoum in 1991, and the M.S.E.E. and the Ph.D. degrees from Purdue University in 1993 and 1999, respectively. He is currently an Associate Professor at the Department of Electrical and Computer Engineering, Purdue School of Engineering and Technology, Indiana University Purdue University Indianapolis (IUPUI). His research interests include image and video compression, image processing, Transmission of compressed Video, Ill posed problems, and medical imaging. Dr. Salama is a member of SPIE, Tau Beta Pi, and Eta Kappa Nu. Maher E. Rizkalla received his Ph.D. in Electrical Engineering from Case Western Reserve University, Cleveland, Ohio in 1985. From Jan. 1985 to Sep. 1986, he was a Visiting Scientist at Argonne National Laboratory, Argonne, IL while being a Visiting Assistant Professor at Purdue University Calumet. Since 1986 he has been with the Department of Electrical and Computer Engineering, Purdue School of Engineering and Technology, Indiana University Purdue University Indianapolis (IUPUI), where he is Professor of Electrical and Computer Engineering. His research interests include solid-state electronics, VLSI design as applied to DSP, electromagnetics, and engineering education. He has published over 100 papers in these areas. He received the outstanding teaching awards in the ECE Department and in the School five times and was the Professor of the Year at Purdue Calumet in 1986. He is the recipient of one NSF grant, and two FIPSE grants, and is COPI of a number of industrial and equipment grants. Dr. Rizkalla is a Senior Member, IEEE, and a Professional Engineer (PE) registered in the State of Indiana. Michael Eckbauer received the M.S.E.E. degree in Electrical Engineering from Indiana University Purdue University Indianapolis (IUPUI) in December 2002. He is currently with GE Medical Systems in Waukesha, Wisconsin.     

一种改进的运动估计快速搜索算法

运动估计是视频压缩中帧间预测编码的关键技术之一。在各个压缩标准中都广泛使用了基于块的运动估计技术。由于运动估计通常具有较大的运算量，因此对压缩性能具有重要的影响。文中分析了视频序列的特点和对现有的快速搜索算法深入理解的基础上提出了一种改进的快速运动估计搜索算法，实验表明该算法对压缩性能有较好的改进。     

基于HEVC六边形运动估计算法的VLSI设计

运动估计是HEVC中计算量最大、耗时最多的模块。为了加速编码过程,设计了适用于HEVC运动估计的六边形搜索算法的VLSI架构。该架构支持HEVC标准中的尺寸可变块设计,并且充分考虑六边形模板的数据复用特点,在PE阵列中使用流水线的组织策略,有效降低了片上缓存的访问次数。采用SMIC 65 nm工艺综合该电路,最高工作频率可达100 MHz,电路规模101 k门,能够满足高清视频（1 920×1 080,60帧/秒）的实时编码要求。     

H.264/AVC中运动估计快速搜索算法研究

针对H.264运动估计模块的运算量较大的问题,业界已经提出各种改进的搜索算法.分析了几种基于H.264的典型快速搜索算法,提出了算法的改进思路.     

基于帧级流水脉动阵列结构的运动估计电路

在将标准的六层Do循环嵌套FSBM算法等效变换成一种新的两层Do循环嵌套算法的基础上,本文提出了三种基于搜索距离分别为P=KN(K≥1),P=N/2和P=N的脉动阵列结构的运动估计电路.上述结构除了支持帧级流水操作外,而且在取得近似100%的阵列流水效率的同时,具有硬件开销小、输入端口数少等特点,可广泛应用于DTV和HDTV等领域.     

一种适合于低代价、低功耗VLSI实现的块匹配运动估值算法

本文给出了一种用于块匹配运动估值的改进的多分辨率望远镜搜索(MRTlcS)算法.它以望远镜的逆向搜索取代了传统的望远镜搜索,这一改进有效地降低了VLSI实现时对片上存储器容量和带宽的要求.此外本文还采用运动跟踪和自适应搜索窗技术来减小运动估值的计算复杂性.适合于低代价、低功耗VLSI实现是新算法的显著特点.模拟结果表明新算法要求的平均运算量仅为MRTlcS算法的30%左右,而仍然可以得到相似的视频解码图质量.本文也给出了新算法和MRTlcS算法用于VLSI实现时的硬件代价和功耗比较.     

基于望远镜搜索的块匹配运动估值的低功耗VLSI结构

在一种基于望远镜搜索的块匹配运动估值的 VL SI实现中 ,对用于加速搜索的传统心动阵列引擎进行了结构上的改进 ,从而能够显著地降低功耗 .方法是使用一种新的块匹配误差计算的提早跳出技术 ,并通过在阵列处理单元中屏蔽操作数来避免不必要的计算操作 .基于算法模拟结果的简单估计表明 :使用新结构搜索引擎的运动估值 ,功耗可降低到原来的 40 %左右 ,而仍然保持着相同的处理速度和相似的视频解码图质量 .     

一种快速高效MPEG-4运动估计硬件结构的研究和实现

提出一种高度并行和多流水线处理的硬件结构,实现MPEG-4视频部分的全搜索块匹配运动估计算法.该硬件结构能实时地通过全搜索块匹配运动估计算法来搜索每个像素块最佳匹配运动向量,具有计算速度高、运动向量准确、较少的内置存储器要求、低运行时钟和低功耗等诸多优点,从而可满足移动视频业务和高清晰视频业务的需求.该硬件结构基于富士通的CE66库实现.     

基于SoPC的视频编码运动估计算法设计

阐述了基于片上可编程系(System on Programmable Chip,soPC)的视频编码运动估计算法,充分发挥了SoPC系统支持软硬件协同设计的优势,利用FPGA硬件实现较复杂的运动估计算法.用NiosⅡCPU软件编程实现三步搜索算法.实验结果表明,该系统具有速度快、集成度高、灵活性好等优点,满足了视频压缩应用的实时性要求.     

基于运动矢量预测的六边形块运动估计搜索算法

在保证图像质量的前提下,为了降低运动估计算法的计算量和搜索点数,提出了一种基于运动场预测的六边形块运动估计搜索算法(PMVHEXBS)。这种算法结合“足够好就停止搜索”的思想和六边形搜索模式(HEXBS)的高速特性,并且在块失真度量中使用部分失真准则(PDC),进一步加快了计算速度。仿真结果显示这种算法和菱形算法(DS)、PM- VFAST算法相比,计算量和搜索点数都有了明显的下降。同时,该算法的图像质量要好于DS算法,和PMVFAST算法相比只有较小的下降。