一种先进运动估计算法的硬件实现

文中介绍了一种先进运动估计处理(MEP)的算法实现。所介绍的MEP用于图像间的运动估计,它计算参考图像在搜索图像区域中不同位移时,两幅图像对应像素点亮度信息的差值之和,并选取最小值作为运动向量。而其硬件实现则采用较先进的处理单元阵列,外挂DSP处理器和外置SRAM存储器,所以算法处理速度可以迅速加快,相反硬件实现的面积也较小。     

H.264编码器中亚像素运动估计的硬件实现

本文在块匹配算法的基础上,提出了一种1／4像素精度的亚像素运动估计的硬件实现方法,在整像素运动估计的基础上实现了半像素和1／4像素最佳匹配点搜索,在空间上具有更高的并行度,硬件实现简洁有效。     

H．264高清视频解码器中参考数据的获取及其硬件实现

提出了一种在H.264高清视频解码芯片设计中读取参考图像数据并用于运动预测的硬件实现方法。硬件设计是基于块尺寸可变的运动预测，根据一种确定的参考图像存储方式，在得到当前块的所有运动预测信息后，实现了运动预测中用于插值运算的参考数据的快速获取，并尽可能节省访问外部RAM的次数与时钟周期，以满足整个设计工程的需要。     

基于Hi3516的监控视频自适应ROI编码

介绍了基于感兴趣区域（ROI）的智能视频监控编码传输基本原理,以及基于单芯片SoC Hi3516的自适应ROI编码软硬件实现方案。在对Hi3516硬件特性进行介绍同时,也给出了利用运动侦测功能和其他手段对ROI进行自动检测,以及利用硬件编码通道进行基于H.264的ROI编码和传输方法。实验结果表明,该系统能实时检测视频中的运动目标并进行ROI编码,使得系统在低码率下也能获得很好的图像重建效果。     

一种便于硬件实现的消锯齿的视频处理方法

文章是针对在隔行到逐行转换过程中产生的运动虚像和锯齿现象,先提出常用的消运动虚像和锯齿的方法,如基于边缘检测的3×3窗口滤波方法、基于运动检测的滤波方法,接着提出一种便于硬件实现的四方向中值滤波取最大值法,该方法除了硬件实现简单、消锯齿效果好,而且具有降噪和保持图像细节的功能。     

基于System Generator的帧间差分运动目标检测算法仿真

该文主要介绍运动目标检测中的帧间差分算法,从硬件实现的角度出发,结合Xilinx公司的Sys-tem Generator系统级建模工具,实现了一种软硬件协同的仿真方式。实验结果表明,该仿真方法简单便捷,用帧间差分算法实现的运动目标检测效果良好。     

视频DSP中运动估计的快速实现

运动估计是运动补偿技术的核心部分。本文在比较了VDSP中几种运动估计算法（光流分析法、块匹配法和象素递归法）的基础上,详细介绍了硬件复杂度较低、易于实现的块匹配法的典型电路。结合这种设计思路,设计出了具有良好前景的VDSP专用芯片。     

周视IRST系统运动目标检测算法的硬件实现

针对当前周视IRST系统中对运动目标检测的需求,综合考虑系统硬件成本和系统实时处理能力需求,研究了基于帧间差分法的运动目标检测算法,并基于FPGA+DSP硬件处理平台,进行了算法的硬件实现与优化,实验结果表明,该信号处理系统检测性能优异,满足目前IRST系统中对运动目标检测的应用需求。     

基于运动目标的二维时间延迟积分红外图像增强

在探讨二维时间延迟积分等红外图像增强技术的基础上,特别针对目标以较大速度运动的情况,提出一种将二维时间延迟积分与目标运动特性相结合的运动运动自适应红外图像增强算法,同时,从系统硬件实时化处理的目的出发,给出了硬件实现方法与具体实验结果,从实验结果看出,所设计系统在图像增强的同时,很好地消除了因目标运动带来的模糊效应.     

一种采用压缩阵列的新型自适应块匹配运动估值器

在视频图像压缩编码中，运动估值计算量巨大、其硬件实现极富挑战性，本文提出一种采用压缩阵列的新型低频滞块匹配运动估值器结构，该结构既能够有效地实现全搜索，又能够实现如三步搜索等快速分层搜索算法，与传统的累加树型结构相比，其运行效率显著提高，而芯片面积进一步减少，在此基础上，本文还提出一种自适应夫匹配和硬件实现方法，使块匹配运算量再降低约１／２－１／４，并以很小的硬件开销进一步降低了延滞。     

一种基于ISS的软硬件协同验证环境

讨论了一种面向SOC设计的基于指令级仿真器(ISS)的软硬件协同验证环境。在该环境中,硬件用硬件描述语言来建模,软件用编程语言来编写,使用指令集仿真器和事件驱动逻辑仿真器分别完成对软硬件的仿真,两个仿真过程使用不同的进程并行进行,并通过进程间通信(IPC)实现两个仿真器之间的信息交互。     

Network/hardware cross-layer evaluation for ROHC and packet aggregation on wireless mesh networks

This paper proposes a profile-based network and hardware co-simulation method to investigate the overall performance and real-timing characteristics of a wireless mesh network (WMN) affected by hardware capabilities, speed and complexity. For the sophisticated algorithms to be assisted by a hardware realization, we adopt the RObust Header Compression (ROHC) and packet aggregation that provide high and reliable data transmission over unstable wireless links, which is proven in the preliminary works. To verify the hardware support needs to get the benefit of the two algorithms, we measure the ROHC processing time from Intel Pentium 4 and RouterBOARD, and identify the deterioration of sensor throughput and successful voice calls under various NS-2 simulation scenarios. The co-simulation method integrates the network level simulator, NS-2 and hardware level simulator, SystemC. In this approach, we first insert the modules of ROHC and packet aggregation algorithms into the network simulator hierarchy, and measure the packet arrival times. Then, the corresponding hardware architecture is designed by SystemC for profiling the hardware delay appeared in encoding and decoding packets. The hardware is suitably designed to reduce the complexity and make a sufficient speedup in the packet processing. Finally, the traced hardware delays are applied into the network level simulator to extract real-timing WMN behaviors changed by the hardware operations in each mesh router.     

System reliability analysis of an N-version programming application

This paper presents a quantitative reliability analysis of a system designed to tolerate both hardware and software faults. The system achieves integrated fault tolerance by implementing N-version programming (NVP) on redundant hardware. The system analysis considers unrelated software faults, related software faults, transient hardware faults, permanent hardware faults, and imperfect coverage. The overall model is Markov in which the states of the Markov chain represent the long-term evolution of the system-structure. For each operational configuration, a fault-tree model captures the effects of software faults and transient hardware faults on the task computation. The software fault model is parameterized using experimental data associated with a recent implementation of an NVP system using the current design paradigm. The hardware model is parameterized by considering typical failure rates associated with hardware faults and coverage parameters. The authors results show that it is important to consider both hardware and software faults in the reliability analysis of an NVP system, since these estimates vary with time. Moreover, the function for error detection and recovery is extremely important to fault-tolerant software. Several orders of magnitude reduction in system unreliability can be observed if this function is provided promptly     

The in-circuit approach to the development of microcomputer-based products

For years, software and hardware development for micro-computer-based products was accomplished by two segregated development efforts. This approach resulted in wasted effort and delays due to inconsistencies between hardware specifications and software implementation at the prototype level. In-circuit emulation, a major breakthrough in microcomputer development systems, has provided the ability to integrate hardware and software development during all phases of the development cycle. The software designer can now work with the prototype hardware as it is being designed by the hardware engineer. In addition, the hardware designer is now able to construct his hardware while working with the actual design software, facilitating debug as hardware development progresses. For the first time, powerful microcomputer development system debug aids can be applied in the user environment.     

并行通道编码EBCOT中MQ编码器的硬件设计

提出了一种适用于JPEG2000标准中并行通道编码的Embedded Block Coding with Optimized Truncation （EBCOT）高速MQ编码器的硬件架构。首先对JPEG2000标准流程的标码流程选择和字节输出等流程进行改进,使之更适应于硬件实现,并提出一种区间重整时对前导零位数的更简洁的判断方法和电路实现,充分利用硬件并行性,提高了编码速度。进而提出了四级流水的MQ编码器硬件架构,有效提高了MQ编码速率,充分满足并行通道编码的要求。     

Virtual Prototyping For Modular And Flexible Hardware-Software Systems

The goal of this work is to develop a methodology for fast prototyping of highly modular and flexible electronic systems including both, software and hardware. The main contribution of this work is the ability to handle a wide range of architectures. We assume that hardware/software partitioning is already made. This stage of the codesign process starts with a virtual prototype, an heterogeneous architecture composed of a set of distributed modules, represented in VHDL for hardware elements and in C for software elements, communicating through communication modules. This work concentrates on a modelling strategy that allow virtual prototype to be used for both cosynthesis (mapping hardware and software modules onto an architectural platform) and cosimulation (that is the joint simulation of hardware and software components) into an unified environment. The main contribution is the use of a multi-view library concept in order to hide specific hardware/software implementation details and communication schemes. In particular this approach addresses the problem of communication between the hardware and software modules.     

数字电路的演化设计方法

电路的演化设计方法是演化硬件研究的一个主要分支,它是开展演化硬件研究的基础,也是演化硬件得以具备自适应和自修复特性的技术前提。首先介绍了数字电路演化设计的理论基础,然后对系统开发所使用的硬件平台进行了描述,最后对电路演化设计的系统流程做了详细描述。为进一步深入到基于演化硬件的数字电路自适应和自修复技术研究打下了基础。     

Hardware/software co-design of digital telecommunication systems

We reflect on the nature of digital telecommunication systems. We argue that these systems require, by nature, a heterogeneous specification and an implementation with heterogeneous architectural styles. CoWare is a hardware/software co-design environment based on a data model that allows to specify, simulate, and synthesize heterogeneous hardware/software architectures from a heterogeneous specification. CoWare is based on the principle of encapsulation of existing hardware and software compilers and special attention is paid to the interactive synthesis of hardware/software and hardware/hardware interfaces. The principles of CoWare are illustrated by the design process of a spread-spectrum receiver for a pager system     

Win32环境下一种通用控制软件的实现方法

介绍了一种通用的控制系统软件的实现方法，该软件架构将复杂的控制系统所有硬件传感器经数学抽象、归类后，使用流对象统一处理，控制软件仅对流操作。所有硬件传感器后台读写用独立线程完成．线程由各自事件同步，同步事件由中断产生，中断由脉冲设备或者定时器产生，软件缓冲区与硬件缓冲区使用临界区对象同步，硬件传感器读写完成后发送用户消息给前台窗口，这样，控制软件中访问硬件的代码段同其他代码段完全独立，特别地，通讯协议等复杂的问题在此软件架构下仅以一条控制函数形式出现。无论控制对象由多少种传感器搭建，无论设备多少，监控软件的架构是一致的，复杂的控制问题就转化为对某类流设备的读写问题。