共查询到19条相似文献,搜索用时 171 毫秒
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HDTV SoC集成芯片的总线设计与验证 总被引:6,自引:4,他引:2
文章提出了一种适合于HDTV SoC的AMBA总线设计方案,并对整个架构进行了详细的验证;实践证明,AMBA总线非常适用于HDTV SoC系统;与用硬件描述语言构建的测试平台相比,软硬件协同的验证方法不但有更高的仿真覆盖率,而且更加高效省时. 相似文献
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用于HDTV视频解码器的高性能SDRAM控制器 总被引:4,自引:1,他引:4
该文提出了一种适用于HDTV视频解码器的高性能SDRAM控制器.通过为SDRAM控制器设置多个端口并集成仲裁功能,该SDRAM控制器可以取代传统的总线 DMA结构,为解码器中的功能单元有效地分配存储器的带宽资源.该文提出的SDRAM控制器内建流水线式的地址和数据路径,配合SDRAM本身流水处理指令的特性,能够无延时地处理各个端口上的存储器访问请求,从而降低了对片上缓存的需求.仿真综合结果表明,该文设计的SDRAM控制器满足HDTV解码的性能要求,且与总线 DMA结构相比,片上缓存容量减少了约70%. 相似文献
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本论文提出一种基于TMS320C6701DSP实现HDTV信源解码器的方案。用C6701实现系统控制、解复用、AC-3音频解码,用STi7000视频解码。与现有的HDTV信源解码方案相比,本方案将核心芯片由三片(系统控制+解复用、视频解码和音频解码)减少到两片,有利于系统集成,代表了HDTV信源解码器的发展方向之一。 相似文献
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基于RISC核的HDTV系统层解码设计 总被引:2,自引:0,他引:2
嵌入式的RISC核已经成为系统集成芯片中最为常用的部件,它不仅完成系统基本的控制功能,还承担一定的算法任务.在MPEG-2MP@HL集成解码芯片中,一种考虑是采用RISC核的控制器完成TS流的解复用、系统信息解码、视频和音频的同步控制等.本文以符合ATSC标准的MPEG-2TS流解复用和系统信息解码为算法对象,研究在片上指令缓存有限的情况下设计嵌入式RISC核时,系统层解码的软/硬件协同设计.通过对系统层解码进行的软件仿真,给出了具体的解码流程和相应的仿真结果,为如何分配片上指令和数据Cache提供了参考,这些结论都已被应用到实际的HDTV系统集成解码芯片的设计中. 相似文献
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提出一种基于ARM ESL平台的软硬件协同的设计方法,并进行了整个AVS解码系统的设计和仿真验证.在具体的软硬件划分中,通过采用硬件加速AVS亮度插值模块,合并了二分与四分之一亮度插值的软件算法, 并用DMA控制器改进插值的硬件结构,从而改善了系统的整体性能.实验中比较十帧720x576的AVS解码图像在原始纯软件环境,同软硬件协同系统的仿真结果.仿真结果说明新的AVS解码系统的体系结构提高了AVS解码系统的整体性能,为AVS系统的软硬件协同设计提供了有益的参照. 相似文献
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在多媒体系统的系统集成芯片(SoC)中,从系统集成芯片工作实时性要求,应用程序和数据尽可能存放在片上存储或Cache,执行方便,处理速度快,就要使用大量的存储部件,使得存储部件的面积和功耗占到整个芯片的很大部分.为了减少片上存储部件,则部分程序和数据移到片外存储,在执行时轮流调进到芯片内,势必增加I/O的开销.因此如何使设计优化是软硬件协同设计中的一个问题.本文以MPEG2集成解码芯片中音频存储优化为例给出了系统集成芯片存储优化的一些方法.包括通过LGDFG(Large Grain Data Flow Graph)模型分析改变程序结构,共享数据空间,改变数据类型以及添加片上SRAM并减少片上Cache容量从而减少系统存储消耗等.这些方法显著地减少系统的存储消耗,降低系统芯片的面积和功耗. 相似文献
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In this paper, an architecture for real-time digital HDTV video decoding is presented. Our architecture is based on a dual decoding datapath controlled in a fixed schedule with an efficient write-back scheme for anchor pictures. The decoding datapath is synchronized at the block (8 × 8 pixels) level. Unlike other decoding approaches such as the slice bar decoding method and the cross-divide method, our scheme reduces memory access contention problem to achieve real-time HDTV decoding without a high cost in overall decoder buffers, architecture, and bus. In comparison to data-flow approaches, our method eliminates the complexity associated with tagged data operations. Our anchor picture storage is organized to minimize page-breaks during memory accesses. Simulation shows that with a relatively low rate 81 MHz clock, our decoder can decode MPEG-2 MP@HL HDTV in real-time, based on an ATSC video format of 1,920 × 1,080 pixels/frame at 30 frames/s, at a bit rate of 18 to 20 Mbps. 相似文献
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Nam Ling Nien-Tsu Wang 《Broadcasting, IEEE Transactions on》2002,48(4):353-360
We present a scheme for real-time digital HDTV video decoding suitable for DVB or ATSC set-top boxes. Our technique is based on a dual decoding datapath controlled in two fixed-scheduling combinations with an efficient memory interface scheme for anchor pictures. Unlike other decoding approaches such as the slice bar decoding method and the crossing-divided method, our scheme reduces memory access contention problem to achieve real-time HDTV decoding without a high cost in overall decoder buffers, architecture, and bus. Our simulation shows that with a relatively low rate 81 MHz clock, our decoder can decode MPEG-2 MP@HL HDTV in real-time, based on a video format of 1920 /spl times/ 1080 pixels/frame at 30 frames/s, at a bit rate of 18-22 Mbps. 相似文献
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Mlynek D.J. Kowalczuk J. 《Proceedings of the IEEE. Institute of Electrical and Electronics Engineers》1995,83(7):1055-1070
The paper provides an overview of the current status in the industry of digitized television including techniques used and their limitations, technological concerns and design methodologies needed to achieve the goals for highly integrated systems. A multiresolution scalable generic HDTV codec based on subband coding is presented, proving the feasibility of VLSI for true HDTV frequency. In addition, a VLSI design methodology is proposed based on programmable processor macrofunctions optimized for the huge amount of data to be processed. The goal was to integrate general VLSI implementation aspects in a specific digital codec system to validate the design methodology for high speed multimedia applications. Digital TV functions can be optimized for encoding and decoding in the same conceptual process and be implemented in silicon in a mole dedicated way using a kind of automated custom design approach allowing enough flexibility 相似文献
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针对高清视频在客户端解码播放过程中存在的CPU占用率高、图像数据拷贝速度低等问题,提出了一种基于GPU解码数据快速拷贝方法。研究了DXVA硬解码方法在视频解码运算过程中的应用,为了消除解码数据在显存拷贝时产生的CPU占用率高现象,利用显存特点和SSE41多媒体指令新特性,设计并实现了视频帧数据快速拷贝方案。实验结果表明,该方法能在满足高清视频实时播放的同时有效降低CPU占用率,且该方法具有一定的实用性。 相似文献
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用软、硬件结合的方法实现对PT2262的解码 总被引:1,自引:0,他引:1
在红外/无线遥控领域,PT2262/2272是目前最常用的芯片之一,从PT2262的编码原理、波形特征入手,通过一个应用实例,结合软、硬件解码各自的优点,提出了具体的解码方法和措施。最后给出了相应的电路原理框图与软件设计流程。 相似文献
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Siracusa R.J. Joseph K. Zdepski J. Raychaudhuri D. 《Selected Areas in Communications, IEEE Journal on》1993,11(1):88-98
The packet-oriented transport approach used in the advanced digital television (ADTV) system for terrestrial HDTV broadcast is described. ADTV achieves robust HDTV delivery on terrestrial simulcast channels via MPEG video compression, prioritization of MPEG data, and `cell-relay' type packet transport in conjunction with a two-tier physical transmission scheme. General design issues relevant to the development of the proposed transport protocol are discussed. ADTV's prioritization algorithm for partitioning MPEG-encoded video into high-priority (HP) and standard-priority (SP) bit streams is outlined. The data transport format supporting these prioritized compressed video bit streams is described. The three principal sublayers of the ADTV transport protocol are discussed in terms of specific functions, impact of system performance, and hardware implementation factors. A proof-of-concept simulation model that incorporates transport encoding and decoding functionality is outlined, and performance evaluation results are given for illustrative transmission scenarios 相似文献
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一种基于SoC的MPEG-4视频解码加速器 总被引:1,自引:0,他引:1
实现了一种应用于系统芯片(SoC)的MPEG-4视频解码加速器。该解码器可完成MPEG-4解码中计算量最大的离散余弦变换(IDCT)、反量化(inverse quantization)和运动补偿叠加(reconstruction)。本文通过算法、总线接口、存储器结构以及硬件开销方面的优化,使得在满足MPEG-4实时解码的基础上,加速器占用SoC系统芯片的总线带宽和硬件面积尽量的小,并有利于存储器的复用。经实验验证,本设计可以对MPEG-4简单层(simple profile)实时解码。 相似文献