Signal-Processing Electronics for a Capacitive Micro-Sensor

An interface circuit in a 0.8-m CMOS process for the on-chip integration of a capacitive micro-sensor used as a microphone is presented. In order to circumvent 1/f noise contributions and to improve the signal/noise ratio, a synchronous modulation-demodulation technique has been applied. For the implementation of this technique, we have studied and designed several functional block, such as modulator with signal conversion, low-noise amplifier, demodulator, etc. To deal with problems related to dispersions of intrinsic capacitance of the sensor, a feedback compensating solution is suggested. The designed circuit has a sensibility of 1200 V/pF, with a minimum detectable capacitance variation of 2 10^-6 pF.1 – 43 bd du 11 Novembre 1918|–     

Design of a New High Speed Amplifier Circuit for the Analog Subsystems

A high speed CMOS amplifier circuit with a new architecture especially suited for analog subsystems and a simple high speed CMOS comparator utilizing the proposed CMOS amplifier circuit are presented. The proposed circuit is simulated using 0.35 m process parameters. The configuration results in several performance improvements over a typical CMOS differential to single ended amplifier. Design details and simulation results show that the newly designed CMOS amplifier circuit and the high speed CMOS comparator are applicable to high speed analog subsystems, especially the flash A/D converter.     

A 20 Gbps inductorless CMOS optical receiver for short-distance VCSEL-based 850 nm optical links

This paper presents a circuit design and experimental results for a 20 Gbps CMOS inductorless optical receiver, a transimpedance amplifier (TIA) and a limiting amplifier, for a vertical-cavity surface emitting laser based 850 nm optical link. The proposed optical receiver apply a power supply noise canceling technique, an additional path from the power supply to the TIA output to generate a reversed phase signal that reduces the power supply noise, and bandwidth enhancement circuit design that dose not require internal inductors. The simulation results shows a power supply rejection ratio of ?96.6 dB at 10 MHz, a total gain of $82.8\,\hbox{dB}\Upomega$ and a ?3 dB bandwidth of 15.5 GHz. A test chip fabricated in 90 nm CMOS technology and demonstrated with a PIN photo-diode, a bandwidth of 17 GHz and a responsibility of 0.53 A/W. The measurement results show a 25 % eye opening and an input sensitivity of ?7.1 dBm at a bit error rate of 10^?12 with a 2⁹ ? 1 pseudo-random test pattern at 20 Gbps. The core circuit of the optical receiver occupies only an area of 0.02 mm².     

CMOS Integrated Lock-in Readout Circuit for FET Terahertz Detectors

In this paper, a switched-capacitor readout circuit topology integrated with a THz antenna and field-effect transistor detector is analyzed, designed, and fabricated in a 0.13-μm standard CMOS technology. The main objective is to perform amplification and filtering of the signal, as well as subtraction of background in case of modulated source, in order to avoid the need for an external lock-in amplifier, in a compact implementation. A maximum responsivity of 139.7 kV/W, and a corresponding minimum NEP of 2.2 nW/√Hz, was obtained with a two-stage readout circuit at 1 kHz modulation frequency. The presented switched-capacitor circuit is suitable for implementation in pixel arrays due to its compact size and power consumption (0.014 mm² and 36 μW).     

A Single-Chip CMOS Transceiver Front-End for DCS-1800 Wireless Communications

This work describes the design and realization of a low voltage single-chip wireless transceiver front-end in a standard 0.25 m CMOS technology. The presented prototype integrates the LNA, down-converters, VCO, quadrature generator, up-converter and pre-amplifier on a single die. A high level of integration is achieved by using a low-IF topology for reception, a direct quadrature up-conversion topology for transmission and an oscillator with on-chip integrated inductor. The final objective of this design is to develop a complete transceiver system for wireless communications at 1.8 GHz that can be built with a minimum of surrounding components: only an antenna, a duplexer, a power amplifier and a baseband signal processing chip. The presented circuit consumes 240 mW from a 2.5 V supply and occupies a die area of 8.6 mm².     

A 2-V CMOS 455-kHz FM/FSK demodulator using feedforward offsetcancellation limiting amplifier

This paper presents a low-voltage low-power IF 455-kHz signal processor that contains a three-stage limiting amplifier and an FM/FSK demodulator. The limiting amplifier uses an on-chip feedforward offset cancellation circuit. The FM/FSK demodulator employs a quadrature detector that is composed of an on-chip phase detector and an external tank phase shifter. The demodulation constant is 20 mV/kHz with masimum ±10-kHz frequency deviation. The IF signal processor that consumes 2.3 mW from a single 2-V power supply demonstrates a high sensitivity of -72 dBm. It occupies an active area of 0.2 mm² using 0.6-μm digital CMOS technology     

The Design of a 2-V 900-MHz CMOS Bandpass Amplifier

A 900 MHz low-power CMOS bandpassamplifier suitable for the applications of RFfront-end in wireless communication receiversis proposed and analyzed. In this design, thetemperature compensation circuit is used tostabilize the amplifier gain so that theoverall amplifier has a good temperaturestability. Moreover, the compact tunablepositive-feedback circuit is connected to theintegrated spiral inductor to generate thenegative resistance and enhance its value. The simple diode varactor circuit isadopted for center-frequency tuning. These twoimproved circuits can reduce the powerdissipation of the amplifier. An experimentalchip fabricated by 0.5 mdouble-poly-double-metal CMOS technologyoccupies a chip area of ; chip area. The measuredresults have verified the performance of thefabricated CMOS bandpass amplifier. Under a2-V supply voltage, the measured quality factoris tunable between 4.5 and 50 and the tunablefrequency range is between 845 MHz and 915 MHz. At , the measured is 20 dB whereas thenoise figure is 5.2 dB in the passband. Thegain variation is less than 4 dB in the rangeof 0–80^°C. The dc powerdissipation is 35 mW. Suitable amplifier gain,low power dissipation, and good temperaturestability make the proposed bandpass amplifierquite feasible in RF front-endapplications.     

The Concept of Operational Rank Extractor

An operational rank extractor (ORE) is introduced in this paper as an operational amplifier having rank extractors at its inputs. This versatile building block can implement a variety of nonlinear transfer functions such as a dead-zone amplifier, a limiter, a full-wave rectifier, and a tri-state comparator (including hysteretic behavior). A 6-input circuit has been implemented in a 2 m CMOS process. The total silicon area is 460 × 100m², and the circuit dissipates 0.7 mW from a single 5 V supply. Various circuit configurations are analyzed theoretically, and experimental results are also provided.     

一种长波红外光导探测器CMOS电路设计

CMOS 电路是高输入阻抗,而长波红外光导探测器是低阻抗,实现低阻抗红外光导探测器与CMOS 电路的良好匹配,是目前长波红外探测器高性能成像的关键技术。文中设计了一种能在低温下工作的低阻抗红外光导探测器CMOS 电路,差分放大器采用正负电源供电,在输入级采用桥式输入方式,该电路第一级采用1M的负反馈电阻实现信号放大,第二级放大采用正端放大方式,输入级、第一级放大、第二级放大均采用直接耦合方式。测试结果表明,该放大器与长波红外低输入阻抗光导探测器连接后能正常工作,总放大倍数大于1 万倍,3 dB 带宽大于4 kHz,等效输入电压噪声小于1.5 V,有效地解决了低阻抗光导探测器与高阻CMOS 电路的匹配问题。     

Analog Circuit Design Methodology in a Low Power RISC Microprocessor

There are various kinds of analog CMOS circuits in microprocessors. IOs, clock distribution circuits including PLL, memories are the main analog circuits. The circuit techniques to achieve low power dissipation combined with high performance in newest prototype chip in the Super H RISC engines are described. A TLB delay can be decreased by using a CAM with a differential amplifier to generate the match signal. The accelerator circuit also helps to speed up the TLB circuit, enabling single-cycle operation. A fabricated 96-mm² test chip with the super H architecture using 0.35-m four metal CMOS technology is capable of 167-MHz operation at 300 Dhrystone MIPS with 2.0-W power dissipation.