掺杂浓度对多晶硅纳米薄膜应变系数的影响

为有效利用多晶硅纳米薄膜研制MEMS压阻器件,本文对LPCVD多晶硅纳米薄膜应变系数与掺硼浓度的关系进行了研究,并利用扫描电镜和X射线衍射实验分析了薄膜的结构特点.结果表明:在重掺杂情况下,纳米薄膜的应变系数明显大于相同掺杂浓度下单晶硅的应变系数,而且掺杂浓度在2.5×1020cm-3左右时,应变系数具有随掺杂浓度升高而增大的趋势.对这种实验结果依据隧道效应原理进行了理论解释,提出了多晶硅压阻特性的修正模型.     

多晶硅纳米薄膜晶界隧道压阻效应

实验表明重掺杂情况下多晶硅纳米薄膜的应变因子比相同浓度单晶硅的大,且随晶粒尺度减小而增大。为使这种特性在压阻器件中得到合理应用,在分析多晶硅能带结构的基础上,阐明了这种特性根源在于流过晶界的隧道电流随应变而变化引起的隧道压阻效应,给出了晶界压阻系数的计算方法,并从理论上解释了多晶硅纳米薄膜压阻特性的实验现象。     

多晶硅薄膜的高温压阻效应

利用LPCVD制备重掺杂多晶硅薄膜,在0～560℃温度范围内对薄膜的压阻效应进行研究,同时对多晶硅薄膜应变系数随温度的变化,以及薄膜的淀积温度与薄膜厚度对应变系数的影响进行了相关的实验研究.结果表明,利用多晶硅材料制作的压敏电阻,其最高工作温度可以达到560℃以上.     

多晶硅隧道压阻模型*

基于陷阱模型,分析了多晶硅能带结构和导电机理,给出了解释隧道压阻效应的等效电路,说明了构成多晶硅压阻效应的内在因素以及隧道压阻效应在其中的作用。综合晶界区域和晶粒中性区两方面压阻效应建立了新的压阻模型——隧道压阻模型。结果表明,掺杂浓度在1020cm-3以上,复合晶界的压阻系数不但大于晶粒中性区的压阻系数,而且随掺杂浓度增加而增大,从而揭示了多晶硅纳米薄膜在重掺杂情况下出现应变因子随掺杂浓增加而增大的重要实验现象的内在机理。     

多晶硅薄膜的高温压阻效应

利用LPCVD制备重掺杂多晶硅薄膜,在0～560℃温度范围内对薄膜的压阻效应进行研究,同时对多晶硅薄膜应变系数随温度的变化,以及薄膜的淀积温度与薄膜厚度对应变系数的影响进行了相关的实验研究.结果表明,利用多晶硅材料制作的压敏电阻,其最高工作温度可以达到560℃以上.     

多晶硅薄膜压阻系数的理论研究

利用应力退耦模型,分别对多晶硅薄膜晶粒中性区和晶界势垒区的压阻系数进行了理论分析,并推导出多晶硅压阻系数的表达式.实验结果表明,利用文中推导出的理论公式所获得的计算值与实验测量结果基本符合,所给出的有关多晶硅压阻系数的理论结果可以作为多晶硅特性分析的理论依据.     

多晶硅薄膜压阻系数的理论研究

利用应力退耦模型,分别对多晶硅薄膜晶粒中性区和晶界势垒区的压阻系数进行了理论分析,并推导出多晶硅压阻系数的表达式.实验结果表明,利用文中推导出的理论公式所获得的计算值与实验测量结果基本符合,所给出的有关多晶硅压阻系数的理论结果可以作为多晶硅特性分析的理论依据.     

双势垒量子阱薄膜压阻效应实验研究

采用分子束外延方法在砷化镓衬底上生长了AlAs/GaAs双势垒量子阱薄膜结构。介绍了量子阱薄膜在单轴压力作用下的压阻实验,测试出薄膜在压力影响下的I-V曲线,并分析了量子阱薄膜压阻效应的成因。通过实验证实了量子阱薄膜具有较高灵敏度的压阻效应,其压阻灵敏度比目前常用的多晶硅的压阻灵敏度提高一个数量级。     

快速热退火多晶硅薄膜压阻特性研究

本文首先系统的研究了用 LPCVD工艺在温度为 625℃、气相硼硅原子比分别为 1.6 × 10~(-3)和2.0×10~(-3)时淀积的、其后又分别经900℃、1050℃、1150℃ 10秒钟快速热退火(RTA)处理的多晶硅薄膜压阻特性.然后,基于上述结果,着重研究了气相硼硅原子比分别为 1.6×10~(-3)、2.0 × 10~(-3)、4.0 ×10~(-3)和5.0 × 10~(-3)时淀积,其后只经1150℃ 10秒钟快速热退火处理的多晶硅薄膜压阻特性.在上述淀积条件下,与900℃ 30分钟常规热退火(FA)相比较,得到了快速热退火的最佳条件.     

厚多晶硅膜饱和掺杂工艺研究

文章主要介绍了通过对厚多晶硅膜进行饱和掺杂来制作低阻值多晶电阻的方法。分析了多晶硅掺杂扩散模式,其中A类扩散模式能够得到较低的多晶电阻。要使杂质以A类扩散模式掺入多晶硅中,需要采用炉管扩散的方式进行长时间的掺杂。受杂质固溶度影响,一定厚度的掺杂多晶硅电阻值是无法无限制降低的,要制作低阻值多晶电阻,需要淀积厚多晶硅薄膜。文章选择炉管扩散的方式,进行低阻值的多晶硅薄膜制作,并通过实验,证实该方法可以得到稳定、均匀、低阻值的多晶硅方块电阻。     

Tunnelling piezoresistive effect of grain boundary in polysilicon nano-films

The experiment results indicate that the gauge factor of highly boron doped polysilicon nanofilm is bigger than that of monocrystalline silicon with the same doping concentration, and increases with the grain size decreasing.To apply the unique properties reasonably in the fabrication of piezoresistive devices, it was expounded based on the analysis of energy band structure that the properties were caused by the tunnel current which varies with the strain change forming a tunnelling piezoresistive effect. Finally, a calculation method of piezoresistance coefficients around grain boundaries was presented, and then the experiment results of polysilicon nanofilms were explained theoretically.     

Piezoresistance in polysilicon

A theoretical model for piezoresistance in polysilicon is described. Grain size, orientation and doping dependence effects are included. Predictions of gauge factor using the model give reasonable agreement with experimental results and enable optimum processing parameters to be chosen for a given grain size.     

Characterization of phosphorus implanted low pressure chemical vapor deposited polycrystalline silicon

Thin (3000–5000Å) low pressure chemically vapor deposited (LPCVD) films of polycrystalline silicon suitable for microelectronics applications have been deposited from silane at 600°C and at a pressure of 0.25 Torr. The films were phosphorus implanted at 150 KeV and electrically characterized with the annealing conditions and film thickness as parameters, over a resistivity range of four orders of magnitude (10³–10⁷Ω/□). Annealing during silox deposition was found to result in a lower film resistivity than annealing done in nitrogen atmosphere. Resistivity measurements as a function of temperature indicate that the electrical activation energy is a linear function of 1/N(N is the doping concentration), changing from 0.056 eV for a doping concentration of 8.9 × 10¹⁸ cm⁻³ to 0.310 eV for doping concentration of 3.3 × 10¹⁸ cm⁻³. The grain boundary trap density was found to have a logarithmically decreasing dependence on the polysilicon thickness, decreasing from 1.3 × 10¹³ cm⁻² for 2850Å polysilicon film to 8.3 × 10¹² cm⁻² for 4500Å polysilicon film.     

Physical Model for the Resistivity and Temperature Coefficient of Resistivity in Heavily Doped Polysilicon

One of the key benefits of using polysilicon as the material for resistors and piezoresistors is that the temperature coefficient of resistivity (TCR) can be tailored to be negative, zero, or positive by adjusting the doping concentration. This paper focuses on optimization of the boron doping of low-pressure chemical vapor deposited polysilicon resistors for obtaining near-zero TCR and development of a physical model that explains quantitatively all the results obtained in the optimization experiments encompassing the doping concentration ranges that show negative, near-zero, and positive TCR values in the polysilicon resistors. The proposed model considers single-crystal silicon grain in equilibrium with amorphous silicon grain boundary. The grain boundary carrier concentration is calculated considering exponential band tails in the density of states for amorphous silicon in the grain boundaries. Comparison of the results from the model shows excellent agreement with the measured values of resistivity as well as TCR for heavily doped polysilicon. It is shown that the trap density for holes in the grain boundary increases as the square root of the doping concentration, which is consistent with the defect compensation model of doping in the amorphous silicon grain boundaries.     

Modeling and optimization of monolithic polycrystalline silicon resistors

The processing parameters of monolithic polycrystalline silicon resistors are examined, and the effect of grain size on the sensitivity of polysilicon resistivity versus doping concentration is studied theoretically and experimentally. Because existing models for polysilicon do not accurately predict resistivity dependence on doping concentration as grain size increases above 600 Å, a modified trapping model for polysilicon with different grain sizes and under various applied biases is introduced. Good agreement between theory and experiments demonstrates that an increase in grain size from 230 to 1220 Å drastically reduces the sensitivity of polysilicon resistivity to doping levels by two orders of magnitude. Such an increase is achieved by modifications of the integrated-circuit processes. Design criteria for the optimization of monolithic polysilicon resistors have also been established based on resistivity control, thermal properties, and device geometry.     

Analysis of the field effect in a metal-oxide-small-grainpolysilicon structure-experimentation and modeling

An analysis of the field effect on small-grained (500-A) thin polysilicon film is carried out to predict the electrical behavior of metal-oxide-polysilicon structures, which depends on the grain size, the doping concentration of the polysilicon layer, and the trap densities at the grain boundaries. A one-dimensional model that is based on the exact numerical solution of Poisson's equation, which takes into account all of these parameters, is developed. Good agreement between experimental and calculated C(V) curves is found     

A 10-s doping technology for the application of low-temperaturepolysilicon TFTs to giant microelectronics

A bucket-type high-density (0.25-1.2-mA/cm²) low-energy (500-2000 V) ion source was utilized for high-speed phosphorus doping directly into a thin polysilicon layer without cap SiO₂. Doping gas with He dilution was selected to reduce etching of polysilicon film. Excimer laser (XeCl, 8 mm×8 mm) pulse annealing was introduced to activate effectively the doped impurity. The combination of these techniques provided a practically low sheet resistance for the TFT source, drain, and gate with a short time doping. The low-temperature polysilicon TFT fabricated with a doping time of 10 s had characteristics comparable to those of that fabricated by a longer time doping or conventional ion implantation, showing the practicality of this technology and its promise for giant microelectronics     

Modeling of accumulation-mode MOSFET's in PolySilicon thin films

An analytic model of p-channel polysilicon MOSFET operating in accumulation mode is presented. The measured device transfer characteristics, for passivated and unpassivated films, are quantitatively explained in terms of leakage, subthreshold, and drive regimes of operation. The observed current swing of 10⁴is shown to result primarily from the gate-voltage-induced mobility enhancement. This enhancement, a unique feature of polysilicon, is quantified via electrostatic shielding and barrier-potential-dependent mobility. The model describes transconductance, drain admittance, and ON/OFF ratio as a function of grain size, trap density and level, film thickness, and doping concentration.