一种低功耗K频段低噪声放大器

基于0.13μm锗硅(SiGe)双极型互补金属氧化物(Bipolar Complementary Metal Oxide Semi-conductor,BiCMOS)工艺,设计制作了一种高增益低功耗K频段低噪声放大器(Low Noise Amplifier,LNA),通过优化晶体管尺寸及利用硅通孔设计高品质因数射极退化电感,降低了LNA噪声.实测结果表明,在1.6 V偏置条件下,该LNA在20 GHz的噪声系数等于1.94 dB,输入1 dB压缩点等于-29.6 dBm;18～21.3 GHz频率范围内,LNA增益大于23.3 dB,S11和S22均小于-10 dB.包含偏置电路功耗在内,芯片功耗仅21 mW,优于其他同等噪声系数的K频段SiGe BiCMOS LNA.该LNA可应用于卫星通信等K频段低功耗接收机系统.     

一种基于MBE差分外延技术的SiGe低噪声放大器

采用MBE差分外延生长SiGe HBT基区,等平面隔离,多晶硅注入、快速退火形成发射区等工艺,实现了SiGe器件的平面集成。基于上述工艺技术研制的SiGe低噪声放大器(LNA),获得了1.7 GHz的带宽,23 dB的增益和3.5 dB的噪声系数。     

基于0.13 μm SiGe BiCMOS工艺的Ka波段低噪声放大器的设计

介绍了一款基于SiGe BiCMOS工艺的Ka波段低噪声放大器(LNA)的设计与测试。分析了毫米波频段硅基集成电路的匹配设计方法,给出了HBT晶体管电流密度与噪声系数的关系,以及最佳噪声偏置点的选取方法。并基于以上方法设计了单级共基共射低噪声放大器,LNA芯片基于Global Foundry 8HP工艺流片验证。测试结果表明,该LNA实现了30~40GHz的-1dB带宽、小于3.5dB的噪声系数以及6.2dBm的1dB压缩输出功率(P-1dB);输入输出反射系数均小于-15dB,中心频率(35GHz)处增益为7.2dB(单级),LNA的直流电流为6.7mA,电源电压为1.8V。     

X波段GaN MMIC低噪声放大器设计

采用SiC衬底0.25 μm AlGaN/GaN高电子迁移率晶体管(HEMT)工艺,研制了一款X波段GaN单片微波集成电路(MMIC)低噪声放大器(LNA).放大器采用三级级联拓扑,第一级采用源极电感匹配,在确保良好的输入回波损耗的同时优化放大器噪声系数;第三级采用电阻电容串联负反馈匹配,在尽量降低噪声系数的前提下,保证良好的增益平坦度、输出端口回波损耗以及输出功率.在片测试表明,在10 V漏级电压、-2 V栅极电压偏置下,放大器静态电流为60 mA,8～12 GHz内增益为22.5 dB,增益平坦度为±1.2 dB,输入输出回波损耗均优于-11 dB,噪声系数小于1.55 dB,1 dB增益压缩点输出功率大于11.9 dBm,其芯片尺寸为2.2 mm×1.1 mm.装配测试表明,噪声系数典型值小于1.6 dB,可承受33 dBm连续波输入功率.该X波段GaN低噪声放大器与高功率放大器工艺兼容,可以实现多功能集成,具有广阔的工程应用前景.     

基于IEEE802.11a标准的SiGe HBT LNA的设计

基于IEEE802.11a标准描述了一款SiGe HBT低噪声放大器(LNA)的设计.为适应该标准的要求,给出了噪声、功率增益及稳定性的优化方法.选用SiGe HBTs作为有源元件,采用T型输入、输出匹配网络设计了电路,并用安捷伦ADS-2006A软件对噪声系数、增益等各项指标进行了仿真.最终在频率为5.2 GHz下,LNA噪声系数F为1.5 dB,增益S21达到12.6 dB,输入、输出反射系数S11和|S22较好,在工作频带内小于-10 dB,LNA性能良好.     

120 nm SiGe BiCMOS 90~100 GHz低噪声放大器

基于IBM8HP 120 nm SiGe BiCMOS工艺,分析了晶体管的最小噪声系数和最大可用增益特性。采用两级Cascode放大器级联结构,研制出一种频带为90~100 GHz的低噪声放大器(LNA)。详细分析了Cascode放大器潜在的自激可能性,采用串联小电阻的方式消除不稳定性。与电磁仿真软件Sonnet联合仿真,结果表明,在频带内,放大器的输入反射系数S11<-18 dB,输出反射系数S22<-12 dB;在94 GHz处,噪声系数为8 dB,增益为14.75 dB,输出1 dB压缩点功率为-7.9 dBm;在1.8 V供电电压下,整个电路的功耗为14.42 mW。该放大器具有低噪声、低功耗的特点。     

一种无电感超宽带低噪声放大器的设计

基于Jazz 0.35 μm SiGe工艺,设计了一款工作在3～10 GHz频带范围内的超宽带低噪声放大器.该放大器采用电阻负反馈结构,并在发射极并联电容,以补偿晶体管高频增益的下降.仿真结果显示,在整个工作频带内,放大器的增益在22.3 dB以上,平坦度保持在1 dB以内,噪声系数在3.7 dB到4.6 dB之间,输入输出反射系数(S_(11)及S_(22))均在-12 dB以下.整个设计最大的优点是没有用到片上电感,使得芯片面积大大缩小,对于商业应用具有极大的吸引力.     

1MHz～40GHz超宽带分布式低噪声放大器设计

为满足宽带系统中低噪声放大器(LNA)宽带的要求,采用0.15μm GaAs赝配高电子迁移率晶体管(PHEMT)工艺,设计了两款1 MHz^40 GHz的超宽带LNA,分别采用均匀分布式放大器结构及渐变分布式放大器结构,电路面积分别为1.8 mm×0.85 mm和1.8 mm×0.8 mm。电磁场仿真结果表明,1 MHz^40 GHz频率范围内,均匀分布式LNA增益为15.3 dB,增益平坦度为2 dB,噪声系数小于5.1 dB;渐变分布式LNA增益为14.16 dB,增益平坦度为1.74 dB,噪声系数小于3.9 dB。渐变分布式LNA较均匀分布式LNA,显著地改善了增益平坦度、噪声性能和群延时特性。     

一种低噪声SiGe微波单片放大电路

介绍了一种利用SiGe技术制作的低噪声SiGe微波单片放大电路(MMIC)。该电路以达林顿结构的形式级联,由两个异质结双极型晶体管(HBT)和4个电阻组成;HBT采用准自对准结构,其SiGe基区为非选择性外延。在1 GHz频率下,电路噪声为1.59 dB,功率增益为14.3 dB,输入驻波比为1.6,输出驻波比为2.0。     

一种具有0.75dB噪声系数的2.3～2.4GHz单片集成低噪声放大器

报道了一种基于0.5μm赝配高电子迁移率晶体管工艺的两级级联结构的微波单片集成低噪声放大器。该低噪声放大器为光纤射频组网技术而研发,采用集总参数元件完成片上输入输出阻抗匹配,节省了芯片面积和成本。在50Ω端口测试条件下,该低噪声放大器在2.3².4GHz的频段内,噪声系数约为0.75dB,增益大于25dB,在3.3V的工作电压下消耗32mA的电流。与同频段同类型的低噪声放大器相比,文中报道的LNA具有突出的低噪声性能,这主要归因于依据晶体管的噪声最优阻抗匹配理论选取了合适的输入级放大管尺寸和一个具有极小寄生电阻的输入匹配网络以及pHEMT管本身优异的低噪声特性。     

A SiGe LC-ladder low noise amplifier with base resistance match,gain and noise flatness for UWB applications

This study presents a 3.1–10.6 GHz ultra-wideband low noise amplifier (UWB LNA) in 0.18 µm SiGe HBT technology. To achieve a good input match, parasitic base resistance in a bipolar transistor and an LC-ladder filter are included into calculations with the common-emitter topology using shunt–shunt capacitive feedback. Both high and flat power gain (S₂₁) and low and flat noise figure (NF) are achieved by adjusting the pole and zero in amplifying stage and quality factors of the fourth-order input network. Design equations for performances such as gain, noise figure and linearity IIP3 are derived especially on gain flatness and noise flatness. LNA dissipates 33 mW power and achieves S₂₁ of 20.65+0.7 dB, NF of 2.79+0.2 dB over the band of 3.1–10.6 GHz. The simulated input third-order intermodulation point (IIP3) is −17 dBm at 10 GHz.     

采用噪声抵消技术的无电感宽带低噪声放大器

设计了一款多用途、宽带、无电感的低噪声放大器。放大器的第1级为单端输入差分输出结构,采用了噪声抵消技术来降低噪声;第2级引入有源感性负载,并通过电阻负反馈来扩展带宽。采用TSMC 130 nm工艺对电路进行仿真,后仿结果表明,在0.4~6.2 GHz带宽范围内,S21为19 dB,噪声系数为1.9~2.5 dB,功耗为9.6 mW,电路核心面积为0.08 mm²。     

（英）CMOS毫米波低功耗超宽带共栅低噪声放大器

本文陈述了一个基于单端共栅与共源共栅级联结构的超宽带低噪声放大器(LNA)。该LNA用标准90-nm RF CMOS工艺实现并具有如下特征：在28.5到39 GHz频段内测得的平坦增益大于10 dB;-3 dB带宽从27到42 GHz达到了15 GHz,这几乎覆盖了整个Ka带;最小噪声系数(NF)为4.2 dB,平均NF在27-42 GHz频段内为5.1 dB;S₁₁在整个测试频段内小于-11 dB。40 GHz处输入三阶交调点(IIP3)的测试值为 2 dBm。整个电路的直流功耗为5.3 mW。包括焊盘在内的芯片面积为0.58*0.48 mm2_。     

A sub-mW 2.9-dB noise figure Inductor-less low noise amplifier for wireless sensor network applications

In this paper, a low power differential inductor-less Common Gate Low Noise Amplifier (CG-LNA) is presented for Wireless Sensor Network (WSN) applications. New Shunt feedback is employed with noise cancellation and Dual Capacitive Cross Coupling (DCCC) techniques to improve the performance of common gate structures in terms of gain, Noise Figure (NF) and power consumption. The shunt feedback path boosts the input conductance of the LNA in current reuse scheme. Both shunt feedback and current reuse bring power dissipation down considerably. In addition, the positive feedback is utilized to cancel the thermal noise of the input transistor. The proposed LNA is designed and simulated in 0.18 µm TSMC CMOS technology. Post layout Simulation results indicate a voltage gain of 16.5 dB with −3 dB bandwidth of 100 MHz–3 GHz. Also third order Input Intercept Point (IIP3) is equal to + 1 dBm. The minimum NF is 2.8 dB and the value of NF at 2.4 GHz is 2.9 dB. S11 is better than −13 dB in whole frequency range. The core LNA consumes 985 µW from a 1.8 V DC voltage supply.     

0.2 GHz～3.2 GHz超宽带低噪声放大器的研制

为了降低接收前端的噪声,设计并制作一种超宽带低噪声放大器。基于负反馈技术和宽带匹配技术,利用Avago ATF-54143 PHEMT晶体管设计了放大器电路。运用ADS2009对重要指标进行仿真及优化。实测结果表明,在0.2 GHz～3.2 GHz这4个倍频程的超宽带范围内,增益大于24 dB,增益平坦小于±2 dB。在0.2 GHz～2GHz内,噪声系数（NF）小于1.2 dB;在2 GHz～2.6 GHz内,NF〈1.5 dB;在2.6 GHz～3.2 GHz内,NF〈2 dB。该放大器性能良好,满足工程应用要求,可用于通信系统的接收机前端。     

Low power high gain CMOS LNA based on inverter cell and self-body bias for UWB receivers

A low-power low-noise amplifier (LNA) utilized a resistive inverter configuration feedback amplifier to achieve the broadband input matching purposes. To achieve low power consumption and high gain, the proposed LNA utilizes a current-reused technique and a splitting-load inductive peaking technique of a resistive-feedback inverter for input matching. Two wideband LNAs are implemented by TSMC 0.18 μm CMOS technology. The first LNA operates at 2–6 GHz. The minimum noise figure is 3.6 dB. The amplifier provides a maximum gain (S₂₁) of 18.5 dB while drawing 10.3 mW from a 1.5-V supply. This chip area is 1.028×0.921 mm². The second LNA operates at 3.1–10.6 GHz. By using self-forward body bias, it can reduce supply voltage as well as save bias current. The minimum noise figure is 4.8 dB. The amplifier provides a maximum gain (S₂₁) of 17.8 dB while drawing 9.67 mW from a 1.2-V supply. This chip area is 1.274×0.771 mm².     

A Reconfigurable Low-Noise Amplifier Using a Tunable Active Inductor for Multistandard Receivers

A reconfigurable low-noise amplifier (LNA) based on a high-value active inductor (AI) is presented in this paper. Instead of using a passive on-chip inductor, a high-value on-chip inductor with a wide tuning range is used in this circuit and results in a decrease in the physical silicon area when compared to a passive inductor-based implementation. The LNA is a common source cascade amplifier with RC feedback. A tunable active inductor is used as the amplifier output load, and for input and output impedance matching, a source follower with an RC network is used to provide a 50 Ω impedance. The amplifier circuit has been designed in 0.18 µm CMOS process and simulated using the Cadence Spectra circuit simulator. The simulation results show a reconfigurable frequency from 0.8 to 2.5 GHz, and tuning of the frequency band is achieved by using a CMOS voltage controlled variable resistor. For a selected 1.5 GHz frequency band, simulation results show S ₂₁ (Gain) of 22 dB, S ₁₁ of ?18 dB, S ₂₂ of ?16 dB, NF of 3.02 dB, and a minimum NF (NFmin) of 1.7 dB. Power dissipation is 19.6 mW using a 1.8 V dc power supply. The total LNA physical silicon area is (200×150) µm².     

兼顾群延时与宽带匹配的SiGe HBT LNA设计

选用SiGe HBT作为电路的有源器件,利用基极串联电感LB与反馈支路、晶体管Miller效应所产生的寄生电容形成的T型匹配网络取得了输入阻抗的良好匹配,并就基极串联电感值对系统群延时的影响进行了讨论,优化LB以满足兼容群延时与宽带匹配的要求.该放大器在3.1～10.6 GHz的带宽内增益达到12.7 dB,增益变化小于等于1.8 dB,噪声小于3.85 dB,群延时小于24 ps,静态功耗仅为6.3 mW.     

A novel simultaneous noise and input VSWR matching technique for broadband LNA

The Simultaneous Noise and Input Voltage Standing Wave Ratio (VSWR) Matching (SNIM) condition for Low Noise Amplifier (LNA), in principle, can only be satisfied at a single frequency. In this paper, by analyzing the fundamental limitations of the narrowband SNIM technique for the broadband application, the authors present a broadband SNIM LNA systematic design technique. The designed LNA guided by the proposed methodology achieves 10 dB power gain with a low Noise Figure (NF) of 0.53 dB. Meanwhile, it provides wonderful input matching of 27 dB across the frequency range of 3∼5 GHz. Therefore, broadband SNIM is realized.     

2dB噪声系数的Ka波段宽带高增益单片低噪声放大器

报道了一种基于商用0.15um赝配高电子迁移率晶体管工艺的单片低噪声放大器,工作频率范围为23~36GHz.它采用自偏置结构.对晶体管栅宽进行了优化设计减小栅极电阻,以得到低的噪声系数.采用吸收回路和加电阻电容网络的直流偏置结构提高电路稳定性,用多谐振点方法和负反馈技术扩展带宽.测试结果表明,其噪声系数低于2.0dB,在31GHz处,噪声系数仅为1.6dB.在整个工作频带范崮内,增益大于26dB,输入回波损耗大于11dB,输出回波损耗大于13dB.36GHz处的ldB压缩点输出功率为14dBm.芯片尺寸为2.4mm×1mm.