Si基双色碲镉汞材料阻挡层生长及表征

报道了Si基中短波双色碲镉汞(MCT)的最新研究进展。阻挡层的生长与表征是获得材料参数精确控制、晶体质量良好的Si基中短波双色HgCdTe材料关键所在。经过阻挡层生长工艺优化,解决了双色HgCdTe材料缺陷直径较大的问题。缺陷直径控制在10 μm以内,缺陷密度控制在2000 cm-3以内。并使用光致发光技术(PL),得到了不易直接获得的双色HgCdTe材料阻挡层的组分信息。     

Si基短波碲镉汞材料分子束外延生长研究

报道了在中波工艺基础上,Si 基碲镉汞分子束外延短波工艺的最新研究进展,通过温度标定、使用反射式高能电子衍射、高温计的在线测量和现有的中波 Si 基碲镉汞温度控制曲线建立及优化了 Si 基碲镉汞短波材料的生长温度控制曲线;获得的 Si 基短波 HgCdTe 材料表面光亮、均匀,表面缺陷密度小于3000 cm －2;基于此技术成功制备出了 Si 基短／中波双色材料。     

Si基HgCdTe材料的电学特性研究

文章研究了Si基分子束外延HgCdTe原生材料、P型退火材料和N型退火材料的霍耳参数、少子寿命等材料电学特性.研究发现,晶格失配导致Si基HgCdTe材料原生材料和N型退火材料迁移率低;Si基原生HgCdTe材料属于高补偿材料,但高补偿性并非材料的固有特性,通过P型退火可使材料变为低补偿材料,迁移率得到提高.采用分子束外延方法制备的3in Si基HgCdTe材料电学性能与GaAs基HgCdTe材料相比,性能还有待提高.改进分子束外延生长工艺提高HgCdTe质量,从而进一步提高迁移率,是Si基外延研究的关键.     

Si基HgCdTe材料的电学特性研究

文章研究了Si基分子束外延HgCdTe原生材料、P型退火材料和N型退火材料的霍耳参数、少子寿命等材料电学特性。研究发现，晶格失配导致Si基HgCdTe材料原生材料和N型退火材料迁移率低；Si基原生HgCdTe材料属于高补偿材料，但高补偿性并非材料的固有特性，通过P型退火可使材料变为低补偿材料，迁移率得到提高。采用分子束外延方法制备的3in Si基HgCdTe材料电学性能与GaAs基HgCdTe材料相比，性能还有待提高。改进分子束外延生长工艺提高HgCdTe质量，从而进一步提高迁移率，是Si基外延研究的关键。     

Si基HgCdTe材料的电学特性研究

文章研究了Si基分子束外延HgCdTe原生材料、P型退火材料和N型退火材料的霍耳参数、少子寿命等材料电学特性。研究发现，晶格失配导致Si基HgCdTe材料原生材料和N型退火材料迁移率低；Si基原生HgCdTe材料属于高补偿材料，但高补偿性并非材料的固有特性，通过P型退火可使材料变为低补偿材料，迁移率得到提高。采用分子束外延方法制备的3in Si基HgCdTe材料电学性能与GaAs基HgCdTe材料相比，性能还有待提高。改进分子束外延生长工艺提高HgCdTe质量，从而进一步提高迁移率，是Si基外延研究的关键。     

Si基碲镉汞分子束外延工艺优化研究

报道了Si基碲镉汞(MCT)分子束外延(MBE)的最新研究进展,通过使用反射式高能电子衍射(RHEED)、高温计的在线测量建立和优化了3 in Si基碲镉汞生长温度曲线;通过二次缓冲层的生长进一步降低了界面能,获得的Si基HgCdTe材料在8μm的厚度下半峰宽达到90.72 arcsec,原生片位错密度(EPD)小于1×107 cm-2;采用此材料成功制备出了高性能的中波Si基1280×1024碲镉汞探测器。     

分子束外延材料表面平整度的研究

分子束外延Si基HgCdTe材料的表面平整度对红外焦平面组件的制备有重要的影响。分子束外延的Si基复合衬底作为HgCdTe分子束外延的衬底材料对最终外延材料的表面平整度的影响较大。本文通过研究工艺过程中各外延因素对Si片和衬底材料表面平整度的影响,通过实验发现脱氧工艺的高温影响最大,其次是Si片自身的表面平整度和外延膜层的厚度。因此要获得低表面平整度的Si基复合衬底必须满足以下三个条件:低Si片表面平整度,低脱附工艺温度,低外延膜厚。     

Si基大面积碲镉汞分子束外延研究

文章报道了Si基碲镉汞分子束外延(MBE)的最新研究进展。尝试用晶向偏角降低高界面应变能的方法,摸索大失配体系中位错的抑制途径,寻找位错密度与双晶半峰宽的对应关系,基本建立了外延材料晶体质量无损检测评价标准,并对外延工艺进行指导。通过上述研究,15~20μm Si基CdTe复合材料双晶半峰宽最好结果为54arcsec,对应位错密度(EPD)小于2×106/cm2,与相同厚度的GaAs/CdTe(211)双晶水平相当,达到或优于国际最好结果。获得的3 in 10μm Si基HgCdTe材料双晶半峰宽最好结果为51arcsec,目前Si基HgCdTe材料已经初步应用于焦平面中波320×240器件制备。     

Si/CdTe复合衬底HgCdTe液相外延材料的生长与性能分析

通过改进推舟液相外延技术,成功地在(211)晶向Si/CdTe复合衬底上进行了HgCdTe液相外延生长,获得了表面光亮的HgCdTe外延薄膜.测试结果表明,(211)Si/CdTe复合衬底液相外延HgCdTe材料组分及厚度的均匀性与常规(111)CdZnTe衬底HgCdTe外延材料相当;位错腐蚀坑平均密度为(5～8)×105 cm-2,比相同衬底上分子束外延材料的平均位错密度要低一个数量级;晶体的双晶半峰宽达到70″左右.研究结果表明,在发展需要低位错密度的大面积长波HgCdTe外延材料制备技术方面,Si/CdTe复合衬底HgCdTe液相外延技术可发挥重要的作用.     

Si/CdTe复合衬底HgCdTe液相外延材料的生长与性能分析

通过改进推舟液相外延技术,成功地在(211)晶向Si/CdTe复合衬底上进行了HgCdTe液相外延生长,获得了表面光亮的HgCdTe外延薄膜.测试结果表明,(211)Si/CdTe复合衬底液相外延HgCdTe材料组分及厚度的均匀性与常规(111)CdZnTe衬底HgCdTe外延材料相当;位错腐蚀坑平均密度为(5～8)×105 cm-2,比相同衬底上分子束外延材料的平均位错密度要低一个数量级;晶体的双晶半峰宽达到70″左右.研究结果表明,在发展需要低位错密度的大面积长波HgCdTe外延材料制备技术方面,Si/CdTe复合衬底HgCdTe液相外延技术可发挥重要的作用.     

Monolithically integrated HgCdTe focal plane arrays

The cost and performance of hybrid HgCdTe infrared (IR) focal plane arrays are constrained by the necessity of fabricating the detector arrays on a CdZnTe substrate. These substrates are expensive, fragile, available only in small rectangular formats, and are not a good thermal expansion match to the silicon readout integrated circuit. We discuss in this paper an IR sensor technology based on monolithically integrated IR focal plane arrays that could replace the conventional hybrid focal plane array technology. We have investigated the critical issues related to the growth of HgCdTe on Si read-out integrated circuits and the fabrication of monolithic focal plane arrays: (1) the design of Si read-out integrated circuits and focal plane array layouts; (2) the low-temperature cleaning of Si(001) wafers; (3) the growth of CdTe and HgCdTe layers on read-out integrated circuits; (4) diode creation, delineation, electrical, and interconnection; and (4) demonstration of high yield photovoltaic operation without limitation from earlier preprocessing such as substrate cleaning, molecular beam epitaxy (MBE) growth, and device fabrication. Crystallographic, optical, and electrical properties of the grown layers will be presented. Electrical properties for diodes fabricated on misoriented Si and readout integrated circuit (ROIC) substrates will be discussed. The fabrication of arrays with demonstrated I–V properties show that monolithic integration of HgCdTe-based IR focal plane arrays on Si read-out integrated circuits is feasible and could be implemented in the third generation of IR systems.     

GaSb: A New Alternative Substrate for Epitaxial Growth of HgCdTe

In this work, GaSb is proposed as a new alternative substrate for the growth of HgCdTe via molecular beam epitaxy (MBE). Due to the smaller mismatch in both lattice constant and coefficient of thermal expansion between GaSb and HgCdTe, GaSb presents a better alternative substrate for the epitaxial growth of HgCdTe, in comparison to alternative substrates such as Si, Ge, and GaAs. In our recent efforts, a CdTe buffer layer technology has been developed on GaSb substrates via MBE. By optimizing the growth conditions (mainly growth temperature and VI/II flux ratio), CdTe buffer layers have been grown on GaSb substrates with material quality comparable to, and slightly better than, CdTe buffer layers grown on GaAs substrates, which is one of the state-of-the-art alternative substrates used in growing HgCdTe for the fabrication of mid-wave infrared detectors. The results presented in this paper indicate the great potential of GaSb to become the next generation alternative substrate for HgCdTe infrared detectors, demonstrating MBE-grown CdTe buffer layers with rocking curve (double crystal x-ray diffraction) full width at half maximum of ～60 arcsec and etch pit density of ～10⁶ cm^?2.     

Fabrication of thin-film cleaved cavities using a bonding andcleaving fixture

A novel method for the fabrication of cleaved-cavities has been developed that uses a copper plate assembly to support semiconductor layers after substrate removal. PbSe layers were grown through a combination of molecular beam epitaxy and liquid phase epitaxy on Si (100) substrates using CaF₂ and BaF₂ buffer layers. After growth the sample was bonded to the edges of a copper plate assembly epilayer down and the BaF₂ buffer layer was etched away allowing for growth substrate removal. This technique allows fabrication of cleaved Fabry-Perot resonant cavities by separating the copper plates after the substrate is removed     

Direct growth of CdZnTe/Si substrates for large-area HgCdTe infrared focal plane arrays

Direct epitaxial growth of high-quality 100lCdZnTe on 3 inch diameter vicinal {100}Si substrates has been achieved using molecular beam epitaxy (MBE); a ZnTe initial layer was used to maintain the {100} Si substrate orientation. The properties of these substrates and associated HgCdTe layers grown by liquid phase epitaxy (LPE) and subsequently processed long wavelength infrared (LWIR) detectors were compared directly with our related efforts using CdZnTe/ GaAs/Si substrates grown by metalorganic chemical vapor deposition (MOCVD). The MBE-grown CdZnTe layers are highly specular and have both excellent thickness and compositional uniformity. The x-ray full-width at half-maximum (FWHM) of the MBE-grown CdZnTe/Si increases with composition, which is a characteristic of CdZnTe grown by vapor phase epitaxy, and is essentially equivalent to our results obtained on CdZnTe/GaAs/Si. As we have previously observed, the x-ray FWHM of LPE-grown HgCdTe decreases, particularly for CdZnTe compositions near the lattice matching condition to HgCdTe; so far the best value we have achieved is 54 arc-s. Using these MBE-grown substrates, we have fabricated the first high-performance LWIR HgCdTe detectors and 256 x 256 arrays using substrates consisting of CdZnTe grown directly on Si without the use of an intermediate GaAs buffer layer. We find first that there is no significant difference between arrays fabricated on either CdZnTe/Si or CdZnTe/GaAs/Si and second that the results on these Si-based substrates are comparable with results on bulk CdZnTe substrates at 78K. Further improvements in detector performance on Si-based substrates require a decrease in the dislocation density.     

MBE growth of HgCdTe on silicon substrates for large-area infrared focal plane arrays: A review of recent progress

We review the rapid progress that has been made during the past three years in the heteroepitaxial growth of HgCdTe infrared detector device structures on Si substrates by molecular-beam epitaxy. The evolution of this technology has enabled the fabrication of high performance, large-area HgCdTe infrared focal-plane arrays on Si substrates. A key element of this heteroepitaxial approach has been development of high quality CdTe buffer layers deposited on Si(112) substrates. We review the solutions developed by several groups to address the difficulties associated with the CdTe/Si(112) heteroepitaxial system, including control of crystallographic orientation and minimization of defects such as twins and threading dislocations. The material quality of HgCdTe/Si and the performance of HgCdTe detector structures grown on CdTe/Si(112) composite substrates is reviewed. Finally, we discuss some of the challenges related to composition uniformity and defect generation encountered with scaling the MBE growth process for HgCdTe to large-area Si substrates.     

Recent Progress in MBE Growth of CdTe and HgCdTe on (211)B GaAs Substrates

Alternate substrates for molecular beam epitaxy growth of HgCdTe including Si, Ge, and GaAs have been under development for more than a decade. MBE growth of HgCdTe on GaAs substrates was pioneered by Teledyne Imaging Sensors (TIS) in the 1980s. However, recent improvements in the layer crystal quality including improvements in both the CdTe buffer layer and the HgCdTe layer growth have resulted in GaAs emerging as a strong candidate for replacement of bulk CdZnTe substrates for certain infrared imaging applications. In this paper the current state of the art in CdTe and HgCdTe MBE growth on (211)B GaAs and (211) Si at TIS is reviewed. Recent improvements in the CdTe buffer layer quality (double crystal rocking curve full-width at half-maximum?≈?30?arcsec) with HgCdTe dislocation densities of ≤10⁶?cm^?2 are discussed and comparisons are made with historical HgCdTe on bulk CdZnTe and alternate substrate data at TIS. Material properties including the HgCdTe majority carrier mobility and dislocation density are presented as a function of the CdTe buffer layer quality.     

Long wavelength infrared, molecular beam epitaxy, HgCdTe-on-Si diode performance

In the past several years, we have made significant progress in the growth of CdTe buffer layers on Si wafers using molecular beam epitaxy (MBE) as well as the growth of HgCdTe onto this substrate as an alternative to the growth of HgCdTe on bulk CdZnTe wafers. These developments have focused primarily on mid-wavelength infrared (MWIR) HgCdTe and have led to successful demonstrations of high-performance 1024×1024 focal plane arrays (FPAs) using Rockwell Scientific’s double-layer planar heterostructure (DLPH) architecture. We are currently attempting to extend the HgCdTe-on-Si technology to the long wavelength infrared (LWIR) and very long wavelength infrared (VLWIR) regimes. This is made difficult because the large lattice-parameter mismatch between Si and CdTe/HgCdTe results in a high density of threading dislocations (typically, >5E6 cm⁻²), and these dislocations act as conductive pathways for tunneling currents that reduce the R_oA and increase the dark current of the diodes. To assess the current state of the LWIR art, we fabricated a set of test diodes from LWIR HgCdTe grown on Si. Silicon wafers with either CdTe or CdSeTe buffer layers were used. Test results at both 78 K and 40 K are presented and discussed in terms of threading dislocation density. Diode characteristics are compared with LWIR HgCdTe grown on bulk CdZnTe.     

异质衬底外延碲镉汞薄膜位错抑制技术进展

分子束外延碲镉汞技术是制备第三代红外焦平面探测器的重要手段,基于异质衬底的碲镉汞材料具有尺寸大、成本低、与常规半导体设备兼容等优点,是目前低成本高性能红外探测器发展中的研究重点。对异质衬底上碲镉汞薄膜位错密度随厚度的变化规律进行了建模计算,结果显示ρ~1/h模型与实验结果吻合度好,异质衬底上原生碲镉汞薄膜受位错反应半径制约,其位错密度无法降低至5×10 6 cm-2以下,难以满足长波、甚长波器件的应用需求。为了有效降低异质外延的碲镉汞材料位错密度,近年来出现了循环退火、位错阻挡和台面位错吸除等位错抑制技术,本文介绍了各技术的原理及进展,分析了后续发展趋势及重点。循环退火和位错阻挡技术突破难度大,发展潜力小,难以将碲镉汞位错密度控制在5×105 cm-2以内。台面位错吸除技术目前已经显示出了巨大的发展潜力和价值,后续与芯片工艺融合后,有望大幅促进低成本长波、中长波、甚长波器件的发展。