Characterization and modeling of bias-stressed InGaP/GaAs collector-up tunneling-collector HBTs fabricated with boron-ion implantation

To characterize and model the degradation of collector-up (C-up) heterojunction bipolar transistors (HBTs), we bias stress InGaP/GaAs C-up tunneling-collector HBTs (TC-HBTs) fabricated under various conditions for etching the collector mesas and of implanting boron ions into the extrinsic emitter. Contrary to the previous reports on reduction in collector current I/sub C/ of bias-stressed emitter-up HBTs fabricated with ion implantation, no I/sub C/ Gummel shift is observed in the case of C-up TC-HBTs, probably due to the lower damage resulting from the lower ion dosage. On the other hand, the base current of the bias-stressed C-up TC-HBTs increases with the decrease of the ion dose and with the increase of the collector mesa undercut under the collector electrode that is also used as an implant mask. We attribute the increased base current to the increased carrier recombination at the extrinsic base surface. Making the area of the emitter-base junction smaller than that of the base-collector junction-using electron-cyclotron resonance plasma etching together with lateral spreading of heavily implanted boron ions-results in a stable current gain even after a 1030-h testing at a junction temperature of 210/spl deg/C and a collector current density of 40/sup 2/kA/cm.     

GaN MOS device using SiO/sub 2/-Ga/sub 2/O/sub 3/ insulator grown by photoelectrochemical oxidation method

We report on a SiO/sub 2/-Ga/sub 2/O/sub 3/ gate insulator stack directly grown on n-type GaN by the photoelectrochemical oxidation method. The resultant MOS devices are fabricated using standard photolithography and liftoff techniques. The effect of annealing temperature on the SiO/sub 2/-Ga/sub 2/O/sub 3//n-type GaN MOS devices is investigated. The properties of high breakdown field, low gate leakage current, and low interface state density are investigated for the MOS devices.     

Long-wavelength In/sub 0.53/Ga/sub 0.47/As-In/sub 0.52/Al/sub 0.48/As large-area avalanche photodiodes and arrays

Large-area (500-/spl mu/m diameter) mesa-structure In/sub 0.53/Ga/sub 0.47/As-In/sub 0.52/Al/sub 0.48/As avalanche photodiodes (APDs) are reported. The dark current density was /spl sim/2.5/spl times/10/sup -2/ nA//spl mu/m/sup 2/ at 90% of breakdown; low surface leakage current density (/spl sim/4.2 pA//spl mu/m) was achieved with wet chemical etching and SiO/sub 2/ passivation. An 18 /spl times/ 18 APD array with uniform distributions of breakdown voltage, dark current, and multiplication gain has also been demonstrated. The APDs in the array achieved 3-dB bandwidth of /spl sim/8 GHz at low gain and a gain-bandwidth product of /spl sim/120 GHz.     

InGaAs-InP metamorphic DHBTs grown on GaAs with lattice-matched device performance and f/sub /spl tau//, f/sub max/>268 GHz

InP-In/sub 0.53/Ga/sub 0.47/As-InP double heterojunction bipolar transistors (DHBTs) were grown on a GaAs substrate using a metamorphic buffer layer and then fabricated. The metamorphic buffer layer is InP - employed because of its high thermal conductivity to minimize device heating. An f/sub /spl tau// and f/sub max/ of 268 and 339 GHz were measured, respectively - both records for metamorphic DHBTs. A 70-nm SiO/sub 2/ dielectric sidewall was deposited on the emitter contact to permit a longer InP emitter wet etch for increased device yield and reduced base leakage current. The dc current gain /spl beta/ is /spl ap/35 and V/sub BR,CEO/=5.7 V. The collector leakage current I/sub cbo/ is 90 pA at V/sub cb/=0.3 V. These values of f/sub /spl tau//, f/sub max/, I/sub cbo/, and /spl beta/ are consistent with InP based DHBTs of the same layer structure grown on a lattice-matched InP substrate.     

Ultrathin Al/sub 2/O/sub 3/ and HfO/sub 2/ gate dielectrics on surface-nitrided Ge

We have studied ultrathin Al/sub 2/O/sub 3/ and HfO/sub 2/ gate dielectrics on Ge grown by ultrahigh vacuum-reactive atomic-beam deposition and ultraviolet ozone oxidation. Al/sub 2/O/sub 3/-Ge gate stack had a t/sub eq//spl sim/23 /spl Aring/, and three orders of magnitude lower leakage current compared to SiO/sub 2/. HfO/sub 2/-Ge allowed even greater scaling, achieving t/sub eq//spl sim/11 /spl Aring/ and six orders of magnitude lower leakage current compared to SiO/sub 2/. We have carried out a detailed study of cleaning conditions for the Ge wafer, dielectric deposition condition, and anneal conditions and their effect on the electrical properties of metal-gated dielectric-Ge capacitors. We show that surface nitridation is important in reducing hysteresis, interfacial layer formation and leakage current. However, surface nitridation also introduces positive trapped charges and/or dipoles at the interface, resulting in significant flatband voltage shifts, which are mitigated by post-deposition anneals.     

547-GHz f/sub t/ In/sub 0.7/Ga/sub 0.3/As-In/sub 0.52/Al/sub 0.48/As HEMTs with reduced source and drain resistance

We fabricated 30-nm gate pseudomorphic channel In/sub 0.7/Ga/sub 0.3/As-In/sub 0.52/Al/sub 0.48/As high electron mobility transistors (HEMTs) with reduced source and drain parasitic resistances. A multilayer cap structure consisting of Si highly doped n/sup +/-InGaAs and n/sup +/-InP layers was used to reduce these resistances while enabling reproducible 30-nm gate process. The HEMTs also had a laterally scaled gate-recess that effectively enhanced electron velocity, and an adequately long gate-channel distance of 12nm to suppress gate leakage current. The transconductance (g/sub m/) reached 1.5 S/mm, and the off-state breakdown voltage (BV/sub gd/) defined at a gate current of -1 mA/mm was -3.0 V. An extremely high current gain cutoff frequency (f/sub t/) of 547 GHz and a simultaneous maximum oscillation frequency (f/sub max/) of 400 GHz were achieved: the best performance yet reported for any transistor.     

High-k Al/sub 2/O/sub 3/ gate dielectrics prepared by oxidation of aluminum film in nitric acid followed by high-temperature annealing

A simple, cost-effective, and room temperature process was proposed to prepare high-k gate dielectrics. An aluminum oxide (Al/sub 2/O/sub 3/) gate dielectric was prepared by oxidation of ultrathin Al film in nitric acid (HNO/sub 3/) at room temperature then followed by high-temperature annealing in O/sub 2/ or N/sub 2/. The substrate injection current behavior and interface trap-induced capacitance were introduced to investigate the interfacial property between the gate dielectric and Si substrate. Al/sub 2/O/sub 3/ gate dielectric MOS capacitors with and without initial SiO/sub 2/ layers were characterized. It was shown that the Al/sub 2/O/sub 3/ gate dielectrics with initial oxide exhibit better electrical properties than those without. The 650/spl deg/C N/sub 2/-POA Al/sub 2/O/sub 3/-SiO/sub 2/ sample with an equivalent oxide thickness of 18 /spl Aring/ exhibits three orders of magnitude reduction in gate leakage current in comparison with the conventional thermal SiO/sub 2/ sample.     

Double heterojunction bipolar transistor in Al/sub x/Ga/sub 1-x/As/GaAs/sub 1-y/Sb/sub y/ system

Double heterojunction bipolar transistors based on the Al/sub x/Ga/sub 1-x/As/GaAs/sub 1-y/Sb/sub y/ system are examined. The base layer consists of narrow band gap GaAs/sub 1-y/Sb/sub y/ and the emitter and collector consist of wider band gap Al/sub x/Ga/sub 1-x/As. Preliminary experimental results show that AlGaAs/GaAsSb/GaAs DHBTs exhibit a current gain of five and a maximum collector current density of 5*10/sup 4/ A/cm/sup 2/.<>     

Ultrathin stacked Si/sub 3/N/sub 4//SiO/sub 2/ gate dielectrics prepared by rapid thermal processing

Ultrathin (58 AA equivalent oxide thickness) stacked Si/sub 3/N/sub 4//SiO/sub 2/ (NO) films with the bottom oxide prepared by rapid thermal oxidation (RTO) in O/sub 2/ and the top nitride deposited by rapid thermal processing chemical vapour deposition (RP-CVD) were fabricated and studied. Results show that the charge trapping and leakage current of the stacked films are comparable to those of pure SiO/sub 2/ and low-field breakdown events are significantly reduced. By scaling down the top nitride thickness the commonly observed flat-band voltage instability of MNOS devices was minimised, but the low-defect property was still preserved.<>     

Turn-on voltage investigation of GaAs-based bipolar transistors with Ga/sub 1-x/In/sub x/As/sub 1-y/N/sub y/ base layers

The fundamental lower limit on the turn on voltage of GaAs-based bipolar transistors is first established, then reduced with the use of a novel low energy-gap base material, Ga/sub 1-x/In/sub x/As/sub 1-y/N/sub y/. InGaP/GaInAsN DHBTs (x/spl sim/3y/spl sim/0.01) with high p-type doping levels (/spl sim/3/spl times/10/sup 19/ cm/sup -3/) and dc current gain (/spl beta//sub max//spl sim/68 at 234 /spl Omega///spl square/) are demonstrated. A reduction in the turn-on voltage over a wide range of practical base sheet resistance values (100 to 400 /spl Omega///spl square/) is established relative to both GaAs BJTs and conventional InGaP/GaAs HBTs with optimized base-emitter interfaces-over 25 mV in heavily doped, high dc current gain samples. The potential to engineer turn-on voltages comparable to Si- or InP-based bipolar devices on a GaAs platform is enabled by the use of lattice matched Ga/sub 1-x/In/sub x/As/sub 1-y/N/sub y/ alloys, which can simultaneously reduce the energy-gap and balance the lattice constant of the base layer when x/spl sim/3y.     

Fully silicided NiSi gate on La/sub 2/O/sub 3/ MOSFETs

We have fabricated the fully silicided NiSi on La/sub 2/O/sub 3/ for n- and p-MOSFETs. For 900/spl deg/C fully silicided CoSi/sub 2/ on La/sub 2/O/sub 3/ gate dielectric with 1.5 nm EOT, the gate dielectric has large leakage current by possible excess Co diffusion at high silicidation temperature. In sharp contrast, very low gate leakage current density of 2/spl times/10/sup -4/ A/cm/sup 2/ at 1 V is measured for 400/spl deg/C formed fully silicided NiSi and comparable with Al gate. The extracted work function of NiSi was 4.42 eV, and the corresponding threshold voltages are 0.12 and -0.70 V for respective n- and p-MOSFETs. Electron and hole mobilities of 156 and 44 cm/sup 2//V-s are obtained for respective n- and p-MOSFETs, which are comparable with the HfO/sub 2/ MOSFETs without using H/sub 2/ annealing.     

Surface leakage currents in SiN/sub x/ passivated AlGaN/GaN HFETs

A novel guarded surface leakage test structure is used to isolate the surface and bulk leakage contributions to gate current in AlGaN/GaN HFETs. Passivation with various recipes of SiN/sub x/ always resulted in the commonly observed increase in gate leakage, which was found to be dominated by bulk leakage through the AlGaN. However, high temperature deposited SiN/sub x/ recipes gave a 1-2 orders reduction in surface leakage, whereas low temperature deposition gave an increase. Gate lag measurements were found to correlate closely with the surface leakage component, giving direct evidence that the key device problem of current slump is associated with current flow at the AlGaN surface.     

A novel InGaP/Al/sub x/Ga/sub 1-x/As/GaAs CEHBT

A new and interesting InGaP/Al/sub x/Ga/sub 1-x/As/GaAs composite-emitter heterojunction bipolar transistor (CEHBT) is fabricated and studied. Based on the insertion of a compositionally linear graded Al/sub x/Ga/sub 1-x/As layer, a near-continuous conduction band structure between the InGaP emitter and the GaAs base is developed. Simulation results reveal that a potential spike at the emitter/base heterointerface is completely eliminated. Experimental results show that the CEHBT exhibits good dc performances with dc current gain of 280 and greater than unity at collector current densities of J/sub C/=21kA/cm/sup 2/ and 2.70/spl times/10/sup -5/ A/cm/sup 2/, respectively. A small collector/emitter offset voltage /spl Delta/V/sub CE/ of 80 meV is also obtained. The studied CEHBT exhibits transistor action under an extremely low collector current density (2.7/spl times/10/sup -5/ A/cm/sup 2/) and useful current gains over nine decades of magnitude of collector current density. In microwave characteristics, the unity current gain cutoff frequency f/sub T/=43.2GHz and the maximum oscillation frequency f/sub max/=35.1GHz are achieved for a 3/spl times/20 /spl mu/m/sup 2/ device. Consequently, the studied device shows promise for low supply voltage and low-power circuit applications.     

Improvements in direct-current characteristics of Al/sub 0.45/Ga/sub 0.55/As-GaAs digital-graded superlattice-emitter HBTs with reduced turn-on voltage by wet oxidation

Heterojunction bipolar transistors (HBTs) having an Al/sub 0.45/Ga/sub 0.55/As-GaAs digital-graded superlattice (DGSL) emitter along with an InGaP sub-emitter are reported. The band diagram of the DGSL emitter is analyzed by using a transfer matrix method and the theoretical result is consistent with the experimental observation that the DGSL emitter smoothes out the potential spike at the emitter-base junction. Such passivated HBTs with a high Al-fraction passivation layer exhibit a small offset voltage of 50 mV, a turn-on voltage of 0.87 V, and a current gain of 385. The HBTs are examined by wet-oxidizing the exposed passivated region under various conditions. Experimental results reveal that the HBTs with an exposed high Al-fraction emitter are sensitive to the ambient air. However, with InGaP capped upon the high Al-fraction emitter, the HBTs exhibit better oxidation quality. The wet oxidation brings forth the most remarkable improvements for the InGaP-capped HBTs when the passivation layer is totally wet oxidized. Furthermore, some devices from the same chip have undergone nitrogen treatment for comparison.     

DRAM plate electrode bias optimization for reducing leakage current in UV-O/sub 3/ and O/sub 2/ annealed CVD deposited Ta/sub 2/O/sub 5/ dielectric films

A new plate biasing scheme is described which allowed the use of 65% higher supply voltage without increasing the leakage current for the UV-O/sub 3/ and O/sub 2/ annealed chemical-vapor-deposited tantalum pentaoxide dielectric film capacitors in stacked DRAM cells. Dielectric leakage was reduced by biasing the capacitor plate electrode to a voltage lower than the conventionally used value of V/sub cc//2. Ta/sub 2/O/sub 5/ films with 3.9 nm effective gate oxide, 8.5 fF//spl mu/m/sup 2/ capacitance and <0.3 /spl mu/A/cm/sup 2/ leakage at 100/spl deg/C and 3.3 V supply are demonstrated.<>     

Al/sub 0.25/Ga/sub 0.75/As/In/sub 0.25/Ga/sub 0.75/As pseudomorphic MODFET with high DC and RF performance

AlGaAs/InGaAs MODFETs having 25% indium in the channel and L/sub G/=0.35 mu m have been fabricated. From DC device characterisation, a maximum saturation current of 670 mA/mm and an extrinsic transconductance of 500 mS/mm have been measured. A maximum unilateral gain cutoff frequency of f/sub c/=205 GHz and a maximum current gain cutoff frequency of f/sub T/=86 GHz have been achieved. Bias dependence of f/sub c/ and f/sub T/ has been measured. At 12 GHz a minimum noise figure of NF=0.8 dB and an associated gain of 11 dB have been measured.<>     

MIM capacitors using atomic-layer-deposited high-/spl kappa/ (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ dielectrics

Metal-insulator-metal (MIM) capacitors with (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ high-/spl kappa/ dielectric films were investigated for the first time. The results show that both the capacitance density and voltage/temperature coefficients of capacitance (VCC/TCC) values decrease with increasing Al/sub 2/O/sub 3/ mole fraction. It was demonstrated that the (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ MIM capacitor with an Al/sub 2/O/sub 3/ mole fraction of 0.14 is optimized. It provides a high capacitance density (3.5 fF//spl mu/m/sup 2/) and low VCC values (/spl sim/140 ppm/V/sup 2/) at the same time. In addition, small frequency dependence, low loss tangent, and low leakage current are obtained. Also, no electrical degradation was observed for (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ MIM capacitors after N/sub 2/ annealing at 400/spl deg/C. These results show that the (HfO/sub 2/)/sub 0.86/(Al/sub 2/O/sub 3/)/sub 0.14/ MIM capacitor is very suitable for capacitor applications within the thermal budget of the back end of line process.     

Temperature dependence of breakdown and avalanche multiplication in In/sub 0.53/Ga/sub 0.47/As diodes and heterojunction bipolar transistors

The avalanche multiplication and impact ionization coefficients in In/sub 0.53/Ga/sub 0.47/As p-i-n and n-i-p diodes over a range of temperature from 20-400 K were measured and shown to have negative temperature dependence. This is contrary to the positive temperature dependence of the breakdown voltage measured on InP/In/sub 0.53/Ga/sub 0.47/As heterojunction bipolar transistors (HBTs) in this and previous works. It is shown that the collector-base dark current and current gain can be the overriding influence on the temperature dependence of breakdown in InP/In/sub 0.53/Ga/sub 0.47/As HBTs and could explain previous anomalous interpretations from the latter.     

Electrical and physical characterization of remote plasma oxidized HfO/sub 2/ gate dielectrics

Bi-layer gate stacks consisting of a HfO/sub 2/ and an interfacial layer are fabricated by remote plasma oxidation (RPO) of Hf metal deposited on an Si substrate. Hf metal is fully oxidized by the RPO even at a temperature as low as 400/spl deg/C due to radical oxygens, leading to an improvement in the quality of HfO/sub 2/ with less impact to the interfacial layer growth. An insufficient oxidation leads to a deterioration of mobility with increasing interface traps and positive bias temperature instability, which is likely caused by the oxygen vacancies acting as traps induced by the remaining Hf metal. The SiO/sub 2/-like interface improves the mobility with reduced interface states. Full oxidation and the controlled SiO/sub 2/-like interface demonstrate RPO as a promising way for gate-stack optimization.     

A 1 cm/spl times/1 cm In/sub 0.53/Ga/sub 0.47/As-In/sub 0.52/Al/sub 0.48/As avalanche photodiode array

We report a 1 cm/spl times/1 cm array of 100 In/sub 0.53/Ga/sub 0.47/As-In/sub 0.52/Al/sub 0.48/As avalanche photodiodes (APD). The average breakdown voltage was 28.7 V with a standard deviation of less than 0.5 V. The distribution of breakdown voltage across the area followed a radial pattern consistent with a slight epitaxial growth nonuniformity. The mean dark current at a gain of 10, or 6.1 A/W, was 10.3 nA, and none of the 100 APDs had a dark current of more than 25 nA. The bandwidth at a gain of 10 was 6.2 GHz, and the maximum gain-bandwidth product was 140 GHz. This technology is ideally suited for next-generation three-dimensional imaging applications.