一种新型2.4 GHz SiGe BiCMOS低噪声放大器

基于窄带低噪声放大器理论,设计了一种2.4 GHz,具有低功耗、低噪声和良好匹配性等优点的新型BiFET结构SiGe BiCMOS低噪声放大器。采用TSMC 0.35μm SiGe BiCMOS工艺库,利用SpectreRF软件的仿真结果显示,该电路具有2.27 dB低噪声系数,11.5 dB正向增益;2 V工作电压下,其功耗仅为6.1 mW。研究结果表明,该低噪声放大器在射频蓝牙系统中具有一定的应用前景。     

基于BiFET结构的宽带低噪声放大器设计

采用0.35 μm siGe BiCMOS工艺实现了双极型晶体管和场效应管结合结构(BiFET结构)的宽带低噪声放大器.电路的输入端采用切比雪夫带通滤波器实现了宽频带范围的阻抗匹配.版图设计的仿真结果表明,在2～3 GHz的频带范围内,该低噪声放大器的噪声系数为2.2～2.7 dB,增益为20～22.7 dB,输入端反射系数为-17～-12 dB.     

S波段雷达接收机前端低噪声放大器

采用0.35μm SiGe BiCMOS工艺设计了用于S波段雷达接收机前端电路的低噪声放大器。对于现代无线接收机来说,其动态范围和灵敏度很大程度上都取决于低噪声放大器的噪声性能和线性度。相对于CMOS工艺来说,SiGe BiCMOS工艺具有更高的截止频率、更好的噪声性能和更高的电流增益,非常适合微波集成电路的设计。该低噪声放大器采用三级放大器级联的结构以满足高达30dB的增益要求。在5V的电源电压下,满足绝对稳定条件,在3GHz-3.5GHz频段内,功率增益为34.5dB,噪声系数为1.5dB,输出1dB功率压缩点为11dBm。     

可用于802.11a／b／g的多频带低噪声放大器设计

本文将介绍一个利用0．35微米SiGe BiCMOS制造工艺所设计出来的多频带低噪声放大器。这个多频带低噪声放大器可操作的频段包括2．4、4．9、5．2及5．7GHz，主要可应用在无线局域网络射频芯片。最后测量出来的结果显示，当第一级晶体管的集极电流偏压在3．8mA时，从2．4GHz到2．5GHz，S11皆小于-27．6dB，而当第一级晶体管的集极电流偏压在比较小的3mA时，从5．1GHz到5．4GHz皆小于-27dB。从5．1GHx到5．4GHz S11则小于-34dB，且从5．7到5．9GHz都小于-21dB。从实验结果我们可清楚地看出，这个低噪声放大器靠着电流大小的改变，就可以让共振频率从某一个频率跳到另一个频率，达到多频带操作的功能。     

一种用于多模宽带无线接收机的2.1-6GHz频段锗硅BiCMOS低噪声放大器设计

本文提出了一种带ESD保护的,用于多模宽带无线接收机的锗硅BiCMOS低噪声放大器。该放大器基于0.18μm锗硅BiCMOS工艺实现,覆盖频率范围达到2.1-6GHz。经过优化噪声模型及电路分析设计,最终的测试结果表明,在整个带宽上低噪声放大器的增益达到12dB,输入三阶交调点为在6GHz处-8dBm,噪声系数为2.3～3.8dB。电路供电电压为2.5V,总功耗为8mW,ESD保护电路可以提供2kV的人体击穿模型电压。     

基于CMOS工艺的一种低功耗高增益低噪声放大器

采用0．18μm CMOS工艺，两级共源结构实现了低功耗高增益的低噪声放大器（LNA）设计。共源结构的级联采用电流共享技术，从而达到低功耗的目的。电路的输入端采用源极电感负反馈实现50欧姆阻抗匹配。同时两级共源电路之间通过串联谐振相级联。该LNA工作在5．2GHz，1.8V电源电压，能提供20dB的增益（S21为20dB），而噪声系数为1．9dB，输入匹配较好，S11为-32dB。     

气象探空雷达中平衡式低噪声放大器设计

为了提高L波段气象探空雷达中射频前端的稳定性,采用ATF54143晶体管设计了一种平衡式结构的低噪声放大器。通过使用ADS软件对该低噪声放大器进行了优化、仿真,并进行了实物加工。实物测试表明,该低噪声放大器带内增益大于15dB,噪声系数小于1dB,稳定性系数大于1。     

一种接收前端三级低噪声放大器的设计

针对单片雷达接收机中对低噪声放大器（LNA）的要求,采用CMOS0．18m工艺设计了三级级联的镜像抑制低噪声放大器。通过在低噪声放大器中接入陷波滤波器,实现对镜像信号的衰减,从而减小了后端混频器电路的设计难度。在ADS中对放大器进行仿真,结果表明：在最大供电电压为5V、信号频段为3．0～3．2GHz时,中频输出225MHz,功率增益31dB,噪声系数（NF）0．5dB,输入输出1—dB点的功率分别为-19．5和11．5dBm,对镜像信号的抑制度达22dB。     

一种接收前端三级低噪声放大器的设计

针对单片雷达接收机中对低噪声放大器（LNA）的要求,采用CMOS0．18,um工艺设计了一个三级级联的镜像抑制低噪声放大器。通过在低噪声放大器中接入限波滤波器,实现对镜像信号的衰减,从而减小了后端混频器电路的设计难度。在ADS中对设计的放大器仿真,其结果为：最大供电电压为5V情况下,信号频段为3．0～3．2GHz,中频输出为225MHz,功率增益≥31dB,噪声系数（FN）≤O．5dB,1dB点的输入／输出功率分别为-19．5dBm和11．5dBm,对镜像信号的抑制度达22dB。     

用于LTE频段的低噪声放大器的仿真与设计

采用场效应晶体管ATF541M4设计了一个工作于LTE第38频段（2570MHz-2620MHz）的低噪声放大器。首先介绍设计低噪声放大器的理论基础,其次在ADS中进行仿真,最后将仿真结果与实测结果进行对比,得出结论。实测结果表明,该低噪声放大器在指定频率范围内噪声系数小于ldB,增益大于13dB,带内波动小于±0．25dB。     

0.5 V ultra-low power wideband LNA with forward body bias technique

An ultra-low power wideband CMOS low noise amplifier (LNA) fabricated in TSMC 0.18 μm RF CMOS process for sub 1 GHz applications is presented. The capacitive cross-coupled LNA with forwardbody- bias (FBB) technique is adopted to achieve wideband input impedance matching and low power, low noise factor. The LNA is tested in the frequency range of 400?900 MHz, and exhibits a voltage gain of 18.5?20.7 dB, and a noise figure of 2.95 dB, drawing only 0.385 mW from 0.5 V power supply.     

A High Gain and Low Supply Voltage LNA for the Direct Conversion Application With 4-KV HBM ESD Protection in 90-nm RF CMOS

A 2.4-GHz low noise amplifier (LNA) for the direct conversion application with high power gain, low supply voltage and plusmn4 KV human body model (HBM) electrostatic discharge (ESD) protection level implemented by a 90-nm RF CMOS technology is demonstrated. At 12.9 mA of current consumption with a supply voltage of 1.0 V, the LNA delivers a power gain of 21.9 dB and the noise figure (NF) of 3.2 dB, while maintaining the input and output return losses below -11 dB and -18.3 dB, respectively. The power gain and NF are only 0.2 dB lower and 0.64 dB higher than those of LNA without ESD protection     

A sub-1-dB NF±2.3-kV ESD-protected 900-MHz CMOS LNA

A sub-1-dB noise figure HBM ESD-protected [-3 kV, 2.3 kV] low noise amplifier (LNA) has been integrated in a 0.35-μm RF CMOS process with on-chip inductors. The sensitivity of the LNA performances to the spread of parasitics associated with package and bondwire has been attenuated by using an inductive on-chip source degeneration. At 920 MHz and P_dc=8.6 mW, the LNA features: noise figure NF=1 dB, input return loss=-8.5 dB, output return loss=-27 dB, power gain G _p=13 dB, input IIP3=-1.5 dBm. At a power dissipation of 5 mW and 17.6 mW, a NF respectively equal to 1.2 dB and 0.85 dB is measured. The CMOS LNA takes 12 pins of a TQFP48 package, an area of 1.0×0.66 mm² (bondwire pads excluded) and it is the first HBM ESD-protected [-3 kV, 2.3 kV] CMOS LNA to break the 1-dB NF barrier     

一种具有新型增益控制技术的CMOS宽带可变增益LNA

高速超宽带无线通信的多标准融合是未来射频器件的发展趋势,该文提出一种基于CMOS工艺、具有新型增益控制技术的宽带低噪声放大器(LNA),采用并联电阻反馈实现宽带输入匹配,并引入噪声消除技术来减小噪声以提高低噪声性能;输出带有新型6位数字可编程增益控制电路以实现可变增益。采用中芯国际0.13m RF CMOS工艺流片,芯片面积为0.76 mm2。测试结果表明LNA工作频段为1.1-1.8 GHz,最大增益为21.8 dB、最小增益8.2 dB,共7种增益模式。最小噪声系数为2.7 dB,典型的IIP3为-7 dBm。     

A novel bipolar-MOSFET low-noise amplifier (BiFET LNA), circuit configuration, design methodology, and chip implementation

This paper proposes a new RF circuit configuration: the Bipolar cascoded with a mosFET (BiFET). Applying the BiFET for low-noise amplifiers (LNAs), we have developed a new BiFET-based design methodology. By using this methodology, a BiFET LNA has been designed based on Jazz Semiconductor Inc.'s SiGe90 BiCMOS process. The packaged chip tested on board has demonstrated a 16-dB power-gain 1.6-dB noise-figure -6.5-dBm input third intercept point while consuming only 3 mW (2.2 V /spl times/ 1.4 mA) in the personal communication system (PCS) band. To our knowledge, this is the lowest current silicon-based LNA reported to date that maintains good PCS band performance.     

深亚微米CMOS低噪声放大器的设计

通过一个符合性能指标的，用于射频接收系统的CMOS低噪声放大性能的设计，讨论了深亚微米MOSFET的噪声情况，并在满足增旋和功耗的前提下，对低噪声放大噪声性能进行分析和优化，该LNA工作在2.5GHz电源电压，直流功耗为25mW，能够提供19dB的增益（S21），而噪声系数仅为2.5dB，同时输入匹配良好，S11为-45dB，整个电路只采用了一个片外电感使电路保持谐振，此设计结果证明CMOS工艺在射频集成电路设计领域具有可观的潜力。     

A 2.7-V 900-MHz CMOS LNA and mixer

A CMOS low-noise amplifier (LNA) and a mixer for RF front-end applications are described. A current reuse technique is described that increases amplifier transconductance for the LNA and mixer without increasing power dissipation, compared to standard topologies. At 900 MHz, the LNA minimum noise figure (NF) is 1.9 dB, input third-order intercept point (IIP3) is -3.2 dBm and forward gain is 15.6 dB. With a 1-GHz local oscillator (LO) and a 900-MHz RF input, the mixer minimum double sideband noise figure (DSB NF) is 5.8 dB, IIP3 is -4.1 dBm, and power conversion gain is 8.8 dB. The LNA and mixer, respectively, consume 20 mW and 7 mW from a 2.7 V power supply. The active areas of the LNA and mixer are 0.7 mm×0.4 mm and 0.7 mm×0.2 mm, respectively. The prototypes were fabricated in a 0.5-μm CMOS process     

Design of UWB switched gain controlled LNA using 0.18 μm CMOS

A switched gain controlled low noise amplifier (LNA) for the 3.1- 4.8 GHz ultra-wideband system is presented. The LNA is fabricated with the 0.18 mum 1P6M standard CMOS process. Measurement of the LNA was performed using an RF probe station. In gain mode, measured results show a noise figure of 4.68-4.97 dB, gain of 12.5-13.9 dB, and input/output return loss higher than 10/8.2 dB. The input IP3 (IIP3) at 4.1 GHz is 1 dBm, and consumes 14.6 mW of power. In bypass mode, measured results show a gain of-7.0 to -8.7 dB, and input/output return loss higher than 10/6.3 dB. The input IP3 at 4.1 GHz is 9.2 dBm, and consumes 1 muW of power.     

2～12 GHz CMOS超宽带低噪声放大器设计

提出了一种基于双反馈电流复用结构的新型CMOS超宽带(UWB)低噪声放大器(LNA),放大器工作在2～12 GHz的超宽带频段,详细分析了输入输出匹配、增益和噪声系数的性能。设计采用TSMC 0.18μm RF CMOS工艺,在1.4 V工作电压下,放大器的直流功耗约为13mW(包括缓冲级)。仿真结果表明,在2～12 GHz频带范围内,功率增益为15.6±1.4 dB,输入、输出回波损耗分别低于-10.4和-11.5 dB,噪声系数(NF)低于3 dB(最小值为1.96 dB),三阶交调点IIP3为-12 dBm,芯片版图面积约为712μm×614μm。     

A CMOS variable gain LNA for UWB receivers

A CMOS variable gain low noise amplifier(LNA) is presented for 4.2-4.8 GHz ultra-wideband application in accordance with Chinese standard.The design method for the wideband input matching is presented and the low noise performance of the LNA is illustrated.A three-bit digital programmable gain control circuit is exploited to achieve variable gain.The design was implemented in 0.13-μm RF CMOS process,and the die occupies an area of 0.9 mm~2 with ESD pads.Totally the circuit draws 18 mA DC current from 1.2 V DC supply,the LNA exhibits minimum noise figure of 2.3 dB,S(1,1) less than -9 dB and S(2,2) less than -10 dB.The maximum and the minimum power gains are 28.5 dB and 16 dB respectively.The tuning step of the gain is about 4 dB with four steps in all.Also the input 1 dB compression point is -10 dBm and input third order intercept point(IIP3) is -2 dBm.