多功能电源监控器MAX707／708及其应用

ＭＡＸ７０７／７０８是一组ＣＭＯＳ监控电路,能够监控电源电压、电池故障。将常用的多功能集成到一片８脚封装的小芯片内,与采用分立元件或单一功能芯片组合的电路相比,大大减小了系统电路的复杂性和元器件数量,显著提高了系统可靠性和精确度。 该系列产品能提供３项功能：①在上电和掉电期间以及电源跌落的情况下可产生复位信号;②一个门限值为１．２５Ｖ的检测器,用于电源故障报警;③手动复位输入功能可以消除抖动。 当电源电压降至４．６５Ｖ （对 ＭＡＸ７０７）或 ４．４Ｖ（对ＭＡＸ７０８）以下时,产生复位输出信号。该系…     

MCS—51单片机在外部电源中断后片内RAM中数据的保护

本文分别京ＨＭＯＳ机型及ＣＨＭＯＳ机型，介绍了ＭＣＳ－５１系列单片机系统在外部电 源中继后，使用备用电源对单片机内剖ＲＡＭ的数据进行保护的原理电话路及程序流程，对断电缆测电路，备用电源供电电路及复位电路进行了原理分析。     

微处理器监控电路MAX791

ＭＡＸ７９１是同类微处理器监控器中，性能很先进的一种。它具有两级掉电检测、手动与自动复位、备用电池自动撤换、ｗａｔｃｈｄｏｇ定时、ＣＭＯＳＲＡＭ或ＥＥＰＲＯＭ写保护等功能。一片就能组成微处理器监控系统，极大地提高了电路的可靠性。文章介绍了其内部原理总体框图和典型应用     

SRAM的掉电保护电路

ＳＲＡＭ的掉电保护电路华中理工大学朱永辉采用ＣＭＯＳＩ艺集成制造的静态随机存取存储器（ＳＲＡＭ），具有功耗低、存取时间短等优点，大大降低了它对系统电源的要求；因而在微机化测量和控制系统中得到了广泛的应用。由于实时性、可靠性、安全性等方面的技术要求，系...     

CMOS电路芯片ESD保护电路设计技术的发展

本文简要地回顾了ＣＭＯＳ电路芯片上ＥＳＤ保护电路设计技术发展概况，给出了在中小规模、大规模及超大规模各阶段的ＣＭＯＳ电路芯片上ＥＳＤ保护电路的主流技术，双寄生的ＳＣＲ结构ＶＬＳＩ ＣＭＯＳ芯片上ＥＳＤ保护电路的最新设计技术，就其ＥＳＤ保护原理、设计技术及取得的成果做了较详细分析和探讨。对于研制高密度、高速度的ＶＬＳＩ ＣＭＯＳ电路。开展高ＥＳＤ失效阈值电压，小几何尺寸及低ＲＣ延迟时间常数保护电路的     

EPSON公司四位单片机选型指南

ＥＰＳＯＮ公司四位单片机选型指南ＳＭＣ６２系列四位单片机ＳＭＣ６２系列单片微处理器是以高效能四位核心ＣＰＵＳＭＣ６２００或ＳＭＣ６２００Ａ为基础组成的成套系列产品。这些产品在ＲＯＭ及ＲＡＭ容量、Ｉ／Ｏ口、片内ＬＣＤ驱动器、电源电压检测电路及高性能外...     

微型复位监控电路

众所周知，复位监控电路的主要目的是提供上电复位，掉电复位，电压跌落复位和看门狗等。为了增加系统的可靠性，大部分数字系统都需要对供电电源和微处理器的活动状态进行监控。复位监控电路可提供复位脉冲使系统稳定，还能防止因时序错误而出现的误操作。本文所描述的Ｍ...     

1．5μm全耗尽CMOS／SIMOX门阵列的研制

本文介绍了可用于高速、高性能抗辐照专用集成电路设计的１．５μｍ薄膜全耗尽ＣＭＯＳ／ＳＩＭＯＸ门阵列母版的研制．较为详细地讨论了ＣＭＯＳ／ＳＩＭＯＸ门阵列基本阵列单元、输入／输出单元、单元库的设计技术以及１．５μｍＣＭＯＳ／ＳＩＭＯＸ门阵列工艺开发过程．该门阵列在５Ｖ电源电压时的单级门延迟时间仅为４３０ｐｓ．     

全MOS管组成的模拟四象限CMOS乘法器

介绍建立于ＭＯＳ管平方特性，由２８个ＣＭＯＳ管组成的四象限ＣＭＯＳ模拟乘法器。以Ｐ阱ＣＭＯＳ工艺制备的电路在电源电压１／３动态范围内，有最大线性误差小于２％的特性，乘法器带宽为６２ｋＨｚ，在±５Ｖ电源电压下，功耗为５ｍＷ，芯片面积为０．４７ｍｍ２。     

新型微处理器监控电路

微处理器监控电路早已得到广泛应用 ,它的发展从分立电路、单一复位功能的三端集成器件到复杂的多功能集成器件 ,在电子技术的各个阶段 ,它都保证了系统的正常运行。本文简要介绍监控电路的基本特性以及一些新型监控复位器件。１电源电压监控电路监控电路最基本的功能就是上电复位(ＰＯＷＥＲ -ＯＮ -ＲＥＳＥＴ)。如果不具备这一功能 ,微处理器系统在上电和电源电压波动时就会出现问题。最简单的上电复位电路是由一个电阻、一个电容和一个二极管组成的 ,其电路连接如图１所示。在上电过程中 ,当电源电压开始上升时 ,ＲＣ电路保持低电平。如…     

一种基于Brokaw带隙基准上电复位电路的设计

为了解决传统上电复位电路电源阈值电压受工艺和温度的影响,提出了以Brokaw带隙基准源为基础结构,由采样电路、电流比较电路和电平转换电路等模块组成的可实现精确复位的上电复位电路。增加带迟滞功能的设计,减小了电源噪声对输出电路的影响。采用0.5μm CMOS工艺并对电路进行仿真。结果显示该电路工作在5 V电源电压,典型工艺和温度下电源阈值为3.19 V,在不同的工艺和温度下对电源阈值的影响较小,误差范围在0.31%~4.7%。     

集成高效率电荷泵的无源电子标签芯片射频前端设计

提出了一种满足ISO/IEC18000-6C标准的无源超高频RFID(射频识别)标签芯片的射频前端结构,该结构包括高效率电荷泵、解调器、调制器、阻抗匹配网络和ESD保护电路。电荷泵通过阈值补偿原理及精确控制补偿电压有效抑制反向漏电流,消除了传统电荷泵中的阈值损失。芯片经TSMC0.18μm CMOS mixed signal工艺流片,实测结果表明,标签最远读距离达7m,写距离为3m,可应用于识别与定位,同时满足HBM2 000V的抗静电指标。     

一种具有掉电数据保持功能的触发器设计

提出了一种用相变器件作为可擦写存储单元的具有掉电数据保持功能的触发器电路.该触发器由四部分组成:具有恢复掉电时数据的双置位端触发器DFF、上电掉电监测置位电路(Power On/Off Reset)、相变存储单元的读写电路(Read Write)和Reset/Set信号产生电路,使之在掉电时能够保存数据,并在上电时完成数据恢复.基于0.13μm SMIC标准CMOS工艺,采用Candence软件对触发器进行仿真,掉电速度达到0.15μs/V的情况下,上电时可以在30ns内恢复掉电时的数据状态.     

A high efficiency charge pump circuit for low power applications

A high efficiency charge pump circuit is designed and realized. The charge transfer switch is biased by the additional capacitor and transistor to eliminate the influence of the threshold voltage. Moreover, the bulk of the switch transistor is dynamically biased so that the threshold voltage gets lower when it is turned on during charge transfer and gets higher when it is turned off. As a result, the efficiency of the charge pump circuit can be improved. A test chip has been implemented in a 0.18 μm 3.3 V standard CMOS process. The measured output voltage of the eight-pumping-stage charge pump is 9.8 V with each pumping capacitor of 0.5 pF at an output current of 0.18 μA, when the clock frequency is 780 kHz and the supply voltage is 2 V. The charge pump and the clock driver consume a total current of 2.9 μA from the power supply. This circuit is suitable for low power applications.     

Leakage Biased pMOS Sleep Switch Dynamic Circuits

In this brief, a low-overhead circuit technique is proposed to simultaneously reduce subthreshold and gate-oxide leakage currents in domino logic circuits. pMOS sleep transistors and a dual threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. A sleep transistor added to the dynamic node strongly turns off all of the high threshold voltage transistors. Similarly, a sleep switch added to the output inverter exploits the initially high subthreshold and gate-oxide leakage currents for placing a circuit into an ultimately low leakage state. The proposed circuit technique lowers the total leakage power by 56.1% to 97.6% as compared to standard dual threshold voltage domino logic circuits. Similarly, a 4.6% to 50.6% reduction in total leakage power is observed as compared to a previously published sleep switch scheme in a 45-nm CMOS technology     

DB-driver: a low power CMOS bootstrapped differential cross-coupled driver

This paper for the first time reports the design of a high speed and low power differential cross-coupled bootstrapped CMOS driver circuit. The circuit design style, based on the proposed differential cross-coupled bootstrapped driver achieves high performance low core area, and fast full-swing operation, even in spite of the fact that the magnitude of the threshold voltage of the CMOS devices cannot be scaled down with the scaling of the power supply voltage. The proposed driver is implemented on 0.13?µm CMOS technology with a power supply of 1.2?V. It is 34% faster and provides 8% less core area when compared to a base-line circuit using an indirect bootstrap technique. In addition, the proposed driver reduces the power consumption by 35%. The superior performance of the proposed circuit over the other differential cross-coupled bootstrapped CMOS driver circuit, for the applications that require high performance, has been verified with post-layout simulation.     

低电压Charge-Recovery逻辑电路的设计

提出了一种新的适用于低电压工作的 sem i- adiabatic逻辑电路—— Dual- Swing Charge- Recovery L ogic(DSCRL) .该电路由 CMOS- latch- type电路及负载驱动电路构成 ,对负载的驱动为 full- adiabatic过程 .DSCRL 的电源为六相双峰值脉冲电源 ,低摆幅脉冲用于驱动负载 ,高摆幅脉冲用于驱动 CMOS- latch- type电路 .降低负载上摆幅时驱动负载的 NMOS管的栅压可以保持不变 ,有效地解决了传统的 adiabatic电路在低电压工作时 charge- re-covery效率降低的问题 .文中比较了 DSCRL 电路与部分文献中的 semi- adiabatic电路的功耗 ,DSCRL 在低电压工作方面     

平板显示器驱动芯片高低电压转换电路

LCD、PDP、VFD等各类平板显示器已越来越受到人们关注与喜爱,但大多数平板显示器需要专用的功率驱动芯片来驱动其发光显示,各类专用功率驱动芯片又离不开高低电压转换电路,高低电压转换电路性能的好坏直接影响到驱动芯片的稳定性和功耗等。通过比较平板显示器驱动芯片的几种典型高低压转换电路,设计出一种带有电流源的CMOS型高低压转换电路,它具有最佳的性能指标,该电路不但可以为平板显示器驱动芯片使用,还可以作为其他各类驱动芯片的高低压转换模块使用,最后给出一种具体的平板显示驱动芯片高压CMOS器件结构。     

Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide leakage current

A circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. PMOS-only sleep transistors and a dual threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. Sleep transistors are added to the dynamic nodes in order to reduce the subthreshold leakage current by strongly turning off all of the high threshold voltage transistors. Similarly, the sleep switches added to the output nodes suppress the voltages across the gate insulating layers of the transistors in the fan-out gates, thereby minimizing the gate tunneling current. The proposed circuit technique lowers the total leakage power by 88 to 97% as compared to the standard dual threshold voltage domino logic circuits. Similarly, a 22 to 44% reduction in the total leakage power is observed as compared to a previously published sleep switch scheme in a 45 nm CMOS technology.     

CMOS exponential function generator

A new CMOS exponential function generator is presented. The proposed circuit is compact, with low power and wide dynamic range. The proposed circuit has been fabricated in a 0.50 /spl mu/m CMOS process. Experimental results show that the output range of the proposed exponential function generator can be more than 15 dB with the linear error less than /spl plusmn/ 0.5 dB. The supply voltage is /spl plusmn/ 1.5 V and the power dissipation is less than 0.4 mW. Experimental results are given to demonstrate the proposed circuit.