外延衬底用CdZnTe晶体进展

文中简要介绍了ＣｄＺｎＴｅ晶体用作ＨｇＣｄＴｅ外延衬底的优点和国内外研究的现状，概括了ＣｄＺｎＴｅ晶体的生长方法及其特状，概括了ＣｄＺｎＴｅ晶体的生长方法及其特点，总结了影响ＣｄＺｎＴｅ晶体生长和晶体质量的因素，提出ＣｄＺｎＴｅ晶体生长中存在的问题和改善晶体质量的措施。     

MOCVD生长的CdZnTe／ZnTe多量子阱的激子光学特性

用常压ＭＯＣＶＤ方法在ＧａＡｓ（１００）衬底上生长了ＣｄＺｎＴｅ／ＺｎＴｅ多量子阱。在室温下，观测到了ＣｄＺｎＴｅ／ＺｎＴｅ多量子阱的三个谱带发光。     

大直径半绝缘4H-SiC单晶生长及表征

采用升华法稳定地生长出7.62 cm半绝缘4H-SiC单晶。通过优化钒掺杂工艺获得了均匀分布的电阻率1011Ω·cm。用激光拉曼光谱仪对晶片进行扫描,结果表明SiC单晶晶型为4H晶型。半绝缘4H-SiC单晶微管密度最好结果小于2 cm-2。用高分辨X射线衍射术表征了7.62 cm 4H-SiC单晶衬底片的结晶质量,（0004）衍射摇摆曲线半峰宽为40＂,说明晶体结晶性较好。     

MOCVD生长的CdZnTe／ZnTe多量子附的激子光学特性

用常压ＭＯＣＶＤ方法在ＧａＡｓ（１００）衬底上生长了ＣｄＺｎＴｅ／ＺｎＴｅ多量子阱。在室温下，观测到了ＣｄＺｎＴｅ／ＺｎＴｅ多量子阱的三个谱带发光。根据ＣｄＺｎＴｅ／ＺｎＴｅ多量子阱的吸收光谱和不同激发光强下的发光光谱，分别归结ＣｄＺｎＴｅ／ＺｎＴｅ多量子阱中观测到的三个发光谱带于覆盖层发光、ｎ＝１的重空穴激子发光及杂质发光。     

大尺寸β-Ga2O3晶片的机械剥离及性能北大核心

针对β—Ga2O3单晶易解理的特性,研究了晶体形状对其（100）主解理面的机械剥离影响。结果表明,棱角较为平缓的体单晶机械剥离时容易出现碎裂,而棱角尖锐的体单晶极易实现机械剥离,并且成功剥离出尺寸大于30mm×10mm的β-Ga2O3单晶片。测试了剥离的β-Ga2O3单晶片微观形貌、表面粗糙度、晶体质量以及位错。结果显示,剥离的β-Ga2O3单晶片具有高的表面质量;原子力显微镜（AFM）测试表明,晶片整体表面粗糙度小于1nm,存在0．5～1nm厚的原子台阶;晶片X射线衍射（XRD）摇摆曲线测试显示,其半高宽（FWHM）值低至50arc-sec,表明晶体具有较高的质量;对晶片进行位错腐蚀,结果显示制备的β-Ga2O3晶片具有较低的位错密度,约为6×10^4cm^-2。     

CdZnTe晶片中Te沉淀相的观察与研究

用透射电子显微镜、红外显微镜、红外光谱及差示扫描量热法观察研究了ＣｄＺｎＴｅ晶体中的Ｔｅ沉淀相．讨论了ＣｄＺｎＴｅ晶体中的Ｔｅ沉淀／夹杂的成因和区别，及其对红外透射比的影响；ＣｄＺｎＴｅ晶体的红外透射光谱和差示扫描量热法结果表明，当晶体中Ｔｅ沉淀相含量（ｗＴｅ）大于０．６ｗｔ％时，其红外透射比低于５５％，并随ｗＴｅ值的增大而下降；此结果可用Ⅱ－Ⅵ族半导体价带内光吸收机制解释．     

采用不同材料坩埚对碲锌镉晶体质量的影响

文中采用热解氮化硼（pBN）坩埚生长Cd0．96Zn0．04Te单晶体，并与采用内壁涂碳的石英坩埚生长的晶体进行了对比分析。本文获得的晶体尺寸为φ45mm×110mm，（111）衬底晶片面积最大可达40mm×30mm，测试分析结果显示：Everson腐蚀坑密度小于2×10^4cm^-2，且分布均匀，无网络状分布结构，与石英熏碳坩埚相比，结构质量有了明显提高；第二相夹杂物尺寸小于2μm，密度为0～1×10^3cm^-3；（111）B晶片的X—ray反射貌相图显示，晶体的结构均匀，完整性较好。上述晶体质量评价指标均优于采用石英熏碳坩埚生长获得的晶体，而且更为重要的是，上述各项指标在同一晶锭的各晶片上基本重复，这说明了单晶具有良好的均匀性，有利于生长均匀的碲镉汞外延层。     

分压控制下高纯,高x值CdZnTe晶体气相生长的研究

尝试采用布里奇曼法生长ＣｄＺｎＴｅ为原材料进行了高ｘ值（ｘ＝０．０４－０．６０）Ｃｄ１－ｘＺｎｘＴｅ晶体在压力控制下的物理气相输运（ＰＶＴ）生长研究，探讨了Ｃｄ源和ＣｄＺｎ合金温度对晶体电学性质的影响。并对ＰＶＴ晶体的纯度、位错坑密度、纵向组成分布以及红外透过率，ＰＬ光谱等进行了检测和分析。     

汽压控制直拉法生长Ⅲ－Ⅴ族材料的生长与特性──与标准液封直拉法材料的比较

利用汽压控制直拉（ＶＣＺ）法，成功地生长了ＩｎＰ和ＧａＡｓ单晶，其位错密度十分低，比液封直拉法生长的单晶要小一个数量级。ＶＰＥＧａＡｓ衬底的剩余应力是ＬＥＣ衬底的１／４。当分子束外延生长时，产生的滑移位错在ＶＣＺ衬底上得到明显改善。在Ｓ掺杂的ＶＰＲＩｎＰ晶体上没有滑移位错。在这种衬底上生长的ＶＰＥＩｎＧａＡｓ外延层显示出几乎没有传播位错，而且漏电流极小。     

InP单晶片翘曲度控制技术研究

InP单晶片受热场及机械损伤的作用而产生翘曲形变,这种形变在外延过程中会产生滑移线,也会影响外延层厚度均匀性,最终影响外延质量,因此必须采取措施对InP衬底的翘曲度加以控制.切割工艺是影响晶片翘曲度的关键,但受InP单晶特性及切割工艺自身的限制,InP切片的翘曲度仍保持在一个较高的水平,不能满足高质量外延的要求,需要采取措施进一步降低翘曲度.讨论了用化学腐蚀方法降低InP单晶切片翘曲度,研究了化学腐蚀液的组分、温度及腐蚀去除量对InP单晶片翘曲度的影响,综合工艺的稳定性和实际操作的便利性及晶片翘曲度的实际测试结果,确定了降低InP单晶片翘曲度的适宜工艺.     

Au/Cd复合电极沉积方法对其与(111)面CdZnTe衬底接触性能的影响

CdZnTe晶片是HgCdTe外延薄膜的理想衬底。为了优化CdZnTe衬底的电学接触性能,作者基于真空蒸发法和磁控溅射法分别在p型导电性CdZnTe晶片(111)B (富碲面)制备Au/Cd复合电极。通过接触粘附试验,研究了复合电极的制备方法对电极与衬底之间的粘附性;利用卢瑟福背散射光谱法（RBS）比较了不同沉积方法下样品的元素深度分布;采用电流-电压(I-V)测试比较了两种制备工艺对Au/Cd复合电极与CdZnTe衬底欧姆接触特性的影响,从而确定了最佳复合电极的制备工艺。     

CdZnTe Substrate Surface Preparation Technology at ASELSAN,Inc. for Molecular Beam Epitaxy Growth of High Quality HgCdTe Epilayers

High quality CdZnTe substrates with 4% ZnTe mole fraction are used for epitaxial growth of HgCdTe infrared detector layers. Molecular Beam Epitaxy (MBE) growth of HgCdTe epilayers requires high quality surface layer with sub-nanometer surface roughness values as well. We report on the development of a CdZnTe substrate surface preparation process for MBE growth of high quality HgCdTe epilayers. Surface preparation processes were performed on both commercially available CdZnTe substrates and substrates obtained from in-house grown CdZnTe boules. We developed a multi-step substrate surface processing flow to achieve sub-nanometer surface roughness, low total thickness variation (TTV), and wax or slurry residue free CdZnTe substrate surfaces. Each process step was optimized with the aim of removing the subsurface damage caused by the previous process step; so that we reduce the amount of damaged layer needed to be etched prior to epitaxy. Our developed surface preparation process can be applicable to commercially available CdZnTe substrates with high surface roughness and high TTV. This process was also optimized for as-cut CdZnTe slices. We are capable of processing typically 25 mm?×?25 mm CdZnTe substrates with achievable surface roughness values (R_rms) down to below 0.5 nm.     

CdZnTe晶体缺陷的交流阻抗谱研究

宽禁带II-VI族半导体化合物碲锌镉(CdZnTe)晶体是制备室温X和γ射线探测器的理想半导体材料,但其晶体缺陷特性对探测器性能有重要的影响,一直是人们研究的热点与难点。文中采用垂直布里奇曼法生长了CdZnTe晶锭,XRD测试表明晶片呈现(111)取向。通过测试样品不同温度下的交流阻抗谱,研究了晶体缺陷的阻抗特性。结果表明,制备的CdZnTe单晶具有负温度系数效应,化学法制备的Au电极与晶片之间形成了欧姆接触,没有出现电极界面和晶界对阻抗谱曲线影响,晶粒导电机制占主导。利用Arrhenius方程拟合曲线获得晶体缺陷的激活能为0.48 eV,表明晶体缺陷以Cd空位为主。     

Impact of Tellurium Precipitates in CdZnTe Substrates on MBE HgCdTe Deposition

State-of-the-art (112)B CdZnTe substrates were examined for near-surface tellurium precipitate-related defects. The Te precipitate density was observed to be fairly uniform throughout the bulk of the wafer, including the near-surface region. After a molecular beam epitaxy (MBE) preparation etch, exposed Te precipitates, small pits, and bumps on the (112)B surface of the CdZnTe wafer were observed. From near-infrared and dark field microscopy, the bumps and small pits on the CdZnTe surface are associated with strings of Te precipitates. Raised bumps are Te precipitates near the surface of the (112)B CdZnTe where the MBE preparation etch has not yet exposed the Te precipitate(s). An exposed Te precipitate sticking above the etched CdZnTe surface plane occurs when the MBE preparation etch rapidly undercuts a Te precipitate. Shallow surface pits are formed when the Te precipitate is completely undercut from the surrounding (112)B surface plane. The Te precipitate that was previously located at the center of the pit is liberated by the MBE preparation etch process.     

Progress in CdZnTe substrate producibility and critical drivers of IRFPA yield originating with CdZnTe substrates

With the goal of maximizing the yield of infrared focal plane arrays (IRFPAs), Santa Barbara Research Center’s (SBRC) Infrared Materials Producibility Program (IRMP) has focused on assessing and improving the quality, yield, and throughput of CdZnTe substrates. A baseline detector lot was fabricated to identify the critical drivers of IRFPA yield coming from the substrates and to evaluate the quality and yield of the current vendor base for CdZnTe substrates. Substrate induced defects and impurities that can potentially affect device performance and operability were carefully mapped out in detail on 44 × 67 mm² size substrates, received from IRMP substrate vendors as well as SBRC. This paper will report on the correlations found between this substrate characterization data base and the IRFPA level defect distributions. Key results from these correlation studies are: (1) extended defects found on the substrates with the Nakagawa etch correlated well with responsivity reduction in the final IRFPA; (2) cross-hatch patterns that were evident in the responsivity map correlated well with similar features seen by x-ray topography on LPE double layers; and (3) a possible correlation of device performance (leakage current at 78K) with copper and lithium impurities in the substrate. Recent initiatives toward improving the quality and yield of the substrate growth process have focused on improving purity in the pre-growth charge preparation, modification of growth parameters to reduce defects and scaling up of the vertical Bridgman growth process from its current 67 mm diameter boule size to 92 mm diameter boules. Promising initial results from the large diameter boule growth process will be shown. The 92 mm diameter CdZnTe boule (6 kg charge) shows two predominant single crystal grains encompassing 75% of boule volume. Defect characterization of boules grown under baseline and modified conditions is discussed.     

碲锌镉晶体的X射线衍射形貌与腐蚀形貌

碲锌镉晶体中存在着各种典型晶体缺陷,其缺陷研究一直倍受关注,X射线衍射形貌术是一种非破坏性地研究晶体材料结构完整性、均匀性的有效方法.采用反射式X射线衍射形貌术对碲锌镉衬底的质量进行了研究,并将衬底的X射线衍射形貌与Everson腐蚀形貌进行了对比分析,碲锌镉衬底的X射线衍射形貌主要有六种特征类型,分别对应不同的晶体结构或缺陷,包括均匀结构、镶嵌结构、孪晶、小角晶界、夹杂、表面划伤,对上述特征类型进行了详细的分析.目前,衬底的X射线衍射形貌主要以均匀结构类型为主,划伤和镶嵌结构缺陷基本已消除,存在的晶体缺陷主要以小角晶界为主.通过对比分析碲锌镉衬底和液相外延碲镉汞薄膜的X射线衍射形貌,发现小角晶界等晶体结构缺陷会延伸到外延层上,碲锌镉衬底质量会直接影响碲镉汞外延层的质量,晶体结构完整的衬底是制备高质量碲镉汞外延材料的基础.     

碲锌镉衬底晶向对碲镉汞薄膜表面形貌的影响

利用定向仪对原生晶片及加工后的碲锌镉衬底的晶向进行比较,观察不同晶向衬底液相外延碲镉汞薄膜的表面形貌,考察了衬底晶向偏差对液相外延碲镉汞薄膜表面形貌的影响。通过进一步的追踪碲锌镉衬底在加工过程中的晶向变化,研究衬底晶向变化的原因和解决方法。研究发现,碲锌镉晶体在初次定向切割后的加工过程中晶向会发生明显变化,而在厚度减薄较大的粗磨工艺后不会发生较大晶向偏差,因此,可将粗磨后衬底的再次定向结果作为进一步筛选碲锌镉衬底的依据,以保证液相外延碲镉汞薄膜的质量。     

碲锌镉晶体定向研究

碲锌镉材料是制备高性能碲镉汞红外焦平面探测器不可或缺的衬底材料.液相外延工艺和分子束外延工艺分别需要使用(111)晶面和(211)晶面碲锌镉衬底制备碲镉汞薄膜材料.低偏角、高精度衬底的选取有利于高质量碲镉汞外延层的获得.介绍了孪晶线快速定向法、使用X射线衍射仪(X-Ray Diffractome-ter,XRD)定向法...     

异质衬底外延碲镉汞薄膜位错抑制技术进展

分子束外延碲镉汞技术是制备第三代红外焦平面探测器的重要手段,基于异质衬底的碲镉汞材料具有尺寸大、成本低、与常规半导体设备兼容等优点,是目前低成本高性能红外探测器发展中的研究重点。对异质衬底上碲镉汞薄膜位错密度随厚度的变化规律进行了建模计算,结果显示ρ~1/h模型与实验结果吻合度好,异质衬底上原生碲镉汞薄膜受位错反应半径制约,其位错密度无法降低至5×10 6 cm-2以下,难以满足长波、甚长波器件的应用需求。为了有效降低异质外延的碲镉汞材料位错密度,近年来出现了循环退火、位错阻挡和台面位错吸除等位错抑制技术,本文介绍了各技术的原理及进展,分析了后续发展趋势及重点。循环退火和位错阻挡技术突破难度大,发展潜力小,难以将碲镉汞位错密度控制在5×105 cm-2以内。台面位错吸除技术目前已经显示出了巨大的发展潜力和价值,后续与芯片工艺融合后,有望大幅促进低成本长波、中长波、甚长波器件的发展。     

碲锌镉衬底重复利用技术研究

芯片制备工艺完成后,给芯片留有一定厚度的衬底,同时利用丝切割技术将多余的碲锌镉衬底取下,并对其进行重复抛光处理。碲锌镉衬底的锌值分布及半高宽(Full Width at Half Maximum, FWHM)测试结果表明,碲锌镉衬底质量较好,可以再次用来制备液相外延碲镉汞薄膜。该薄膜经过标准探测器芯片工艺后,性能合格。该研究使原本要完全去除的衬底得以重复利用,提高了碲锌镉衬底的利用率,降低了探测器的制造成本。