Computation sharing programmable FIR filter for low-power and high-performance applications

This paper presents a programmable digital finite-impulse response (FIR) filter for high-performance and low-power applications. The architecture is based on a computation sharing multiplier (CSHM) which specifically targets computation re-use in vector-scalar products and can be effectively used in the low-complexity programmable FIR filter design. Efficient circuit-level techniques, namely a new carry-select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. A 10-tap programmable FIR filter was implemented and fabricated in CMOS 0.25-/spl mu/m technology based on the proposed architectural and circuit-level techniques. The chip's core contains approximately 130 K transistors and occupies 9.93 mm/sup 2/ area.     

A Reconfigurable Channel Filter for Software Defined Radio Using RNS

This paper presents a high-speed FIR channel filter using residue number system (RNS) whose frequency response can be reconfigured to adapt to a multitude of channel filtering specifications of a multi-standard software defined radio (SDR) receiver. The channel filters in the channelizer of an SDR extract multiple narrowband channels corresponding to different communication standards from the wideband input signal. The proposed architecture has been synthesized on TSMC 0.18 μm CMOS standard cell technology. Synthesis result shows that the proposed reconfigurable FIR channel filter, for a Digital Advanced Mobile Phone Systems (D-AMPS) example, offers speed improvement of 42% and AT complexity reduction of 26% over existing reconfigurable FIR method.     

A Tutorial on Multiplierless Design of FIR Filters: Algorithms and Architectures

Finite impulse response (FIR) filtering is a ubiquitous operation in digital signal processing systems and is generally implemented in full custom circuits due to high-speed and low-power design requirements. The complexity of an FIR filter is dominated by the multiplication of a large number of filter coefficients by the filter input or its time-shifted versions. Over the years, many high-level synthesis algorithms and filter architectures have been introduced in order to design FIR filters efficiently. This article reviews how constant multiplications can be designed using shifts and adders/subtractors that are maximally shared through a high-level synthesis algorithm based on some optimization criteria. It also presents different forms of FIR filters, namely, direct, transposed, and hybrid and shows how constant multiplications in each filter form can be realized under a shift-adds architecture. More importantly, it explores the impact of the multiplierless realization of each filter form on area, delay, and power dissipation of both custom (ASIC) and reconfigurable (FPGA) circuits by carrying out experiments with different bitwidths of filter input, design libraries, reconfigurable target devices, and optimization criteria in high-level synthesis algorithms.     

Domain Specific Reconfigurable Processing Core Architecture for Digital Filtering Applications

This paper presents a reconfigurable processing core architecture targeted for digital filtering applications. The architecture can be configured to execute linear phase FIR filter, DLMS adaptive FIR filter, (I)FFT, and 2D-(I)DCT with high performance and low energy consumption by reducing heavy routing resources used extensively in other reconfigurable architectures. The pipeline depth of the multipliers in the processing core is locally controlled so that power consumption is reduced by minimizing unnecessary register switching is saved. We have shown that the proposed processing core consumes less energy and has better or comparable performance than that of the existing reconfigurable architectures proposed in academia and industry, that have been tailored for these applications. The circuit is designed in 0.35-m CMOS processing technology with 3.3 V supply voltage.Sangjin Hong received the B.S. and M.S. degrees in EECS from the University of California, Berkeley and his Ph.D in EECS from the University of Michigan, Ann Arbor. He is currently with the department of Electrical and Computer Engineering at Stony Brook University - State University of New York. Before joining SUNY, he has worked at Ford Aerospace Corp. Computer Systems Division as a systems engineer. He also worked at Samsung Electronics in Korea as a technical consultant. His current research interests are in the areas of low power reconfigurable SoC design and optimization for DSP and wireless communication systems. He has served as a member of technical committee and track chair for numerous IEEE technical conferences.Shu-Shin Chin was born in Kaohsiung, Taiwan, ROC, in 1974. He received his M.S. and Ph.D degrees in electrical and computer engineering from Stony Brook University—State University of New Yorkin 1999 and 2004, respectively. His research interests include low-power digital circuits, and coarse-grained reconfigurable architectures for high-performance DSP systems.     

A Reconfigurable Mixed-Signal VLSI Implementation of Distributed Arithmetic Used for Finite-Impulse Response Filtering

A reconfigurable implementation of distributed arithmetic (DA) for post-processing applications is described. The input of DA is received in digital form and its analog coefficients are set by using the floating-gate voltage references. The effect of the offset and gain errors on DA computational accuracy is analyzed, and theoretical results for the limitations of this design strategy are presented. This architecture is fabricated in a 0.5-mum CMOS process, and configured as a 16-tap finite impulse response (FIR) filter to demonstrate the reconfigurability and computational efficiency. The measurement results for comb, low-pass, and bandpass filters at 32/50-kHz sampling frequencies are presented. This implementation occupies around 1.125 mm² of die area and consumes 16 mW of static power. The filter order can be increased at the cost of 0.011 mm² of die area and 0.02 mW of power per tap.     

Design of FIR filter ISOTA with the aid of genetic algorithm

The field of digital signal processing has been receiving justified attention over the years because of a number of reasons including sophisticated algorithms, high computational speed and wider area of applications. In connection to this, design of finite impulse response (FIR) filter has drawn the attention of researchers throughout the globe. A number of promising developments has been carried out over the last few decades which emphasize on the design of hardware efficient filter structure. In this paper, a new technique of FIR filter design has been addressed by virtue of genetic algorithm. Filter coefficients have been searched over the discrete space in such a way that the architecture consists of shifts and only two adders. As a matter of fact, the proposed FIR filter involving shift and only two additions (ISOTA) results in minimal hardware cost during its implementation. This has been illustrated by means of a few example filters in this work. Some of the recently proposed FIR ISOTA filters have also been taken for the purpose of comparison. Finally, the proposed filter has been implemented on Altera Cyclone IV FPGA board.     

A flexible adaptive FIR filter VLSI IC

The architecture and features of the Motorola DSP56200 are described. The DSP56200 is an algorithm-specific cascadable digital signal processing peripheral designed to perform the computationally intensive tasks associated with finite impulse response (FIR) and adaptive FIR digital filtering applications. The DSP56200 is implemented in high-performance, low-power 1.5-μm HCMOS technology and is available in a 28-pin DIP package. The on-chip computation unit includes a 97.5-ns 24-bit×24-bit coefficient RAM, and a 256-bit×16-bit data RAM. Three modes of operation allow the part to be used as a single, dual, or single adaptive FIR filter, with up to 256 taps per chip. In the adaptive mode, the part performs the FIR filtering and least-mean-square (LMS) coefficient update operations for a single tap in 195 ns, permitting use of the part as a 19-kHz sampling rate, 256-tap adaptive FIR filter. A programmable DC tap, coefficient leakage, and adaptation coefficient parameters in the adaptive FIR mode allow the DSP56200 to be used in a wide variety of adaptive FIR filtering applications. The performance of the part in an echo canceler configuration is presented. Typical applications of the part are also described     

A reconfigurable 8 GOP ASIC architecture for high-speed datacommunications

A flexible and reconfigurable signal processing ASIC architecture has been developed, simulated, and synthesized. The proposed architecture compares favorably to classical DSP and FPGA solutions. It differs from general-purpose reconfigurable computing (RC) platforms by emphasizing high-speed application-specific computations over general-purpose flexibility. The proposed architecture can he used to realize any one of several functional blocks needed for the physical layer implementation of data communication systems operating at symbol rates in excess of 125 Msymbols/s. Multiple instances of a chip based on this architecture, each operating in a different mode, can be used to realize the entire physical layer of high-speed data communication systems. The architecture features the following modes (functions): real and complex FIR/IIR filtering, least mean square (LMS)-based adaptive filtering, discrete Fourier transforms (DFT), and direct digital frequency synthesis (DDFS) at up to 125 Msamples/s. All of the modes are mapped onto a common, regular data path with minimal configuration logic and routing. Multiple chips operating in the same mode can be cascaded to allow for larger blocks     

高速FIR滤波器的流水线结构

通过一个13阶线性相位的平方根升余弦滚降FIR数字滤波器的结构设计，介绍了如何应用流水线技术来设计高速FIR滤波器。考虑到FPGA的容量问题，对采用流水线技术之后的FIR滤波器占用的硬件资源进行了分析，得出一些结论。     

基于MATLAB的高性能半带滤波器设计

在数字滤波器的设计中,为了能够有效地进行抽取滤波,往往采用多级抽取的方法。文中引入一种半带FIR（有限冲激响应）滤波器来实现多级抽取。半带滤波器是一种特殊的低通FIR数字滤波器,它的通带和阻带关于二分之一Nyquist频率对称,因而有近一半的滤波器系数为0,所以用它来实现数字滤波可以大幅度地减少运算量,有利于滤波器的实时实现。半带FIR滤波器主要应用于多速率系统中,可以提高系统的效率。剖析了半带FIR滤波器的原理、性质及实现的方法,给出了基于MATLAB和QuartusⅡ联合的半带FIR滤波器的设计仿真过程,并对结果进行了分析。     

Two's complement computation sharing multiplier and its applications to high performance DFE

We present a novel computation sharing multiplier architecture for two's complement numbers that leads to high performance digital signal processing systems with low power consumption. The computation sharing multiplier targets the reduction of power consumption by removing redundant computations within system by computation reuse. Use of computation sharing multiplier leads to high-performance finite impulse response (FIR) filtering operation by reusing optimal precomputations. The proposed computation sharing multiplier can be applicable to adaptive and nonadaptive FIR filter implementation. A decision feedback equalizer (DFE) was implemented based on the computation sharing multiplier in a 0.25-/spl mu/ technology as an example of an adaptive filter. The performance and power consumption of the DFE using a computation sharing multiplier is compared with that of DFEs using a Wallace-tree and a Booth-encoded multiplier. The DFE implemented with the computation sharing multiplier shows improvement in performance over the DFE using a Wallace-tree multiplier, reducing the power consumption significantly.     

A New Low-Power Architecture Design for Distributed Arithmetic Unit in FIR Filter Implementation

In this article, an improved Distributed Arithmetic (DA) architecture is proposed, in which the high power consumed by adder units is relocated in the system to reduce the switching activity and total power needed. We used the concept of Time Domain Activity Duration Function (ADF) in architectural-level modification of target units at dynamic operating conditions. The proposed DA exploits the circuit activity, and the adder units are used in minimum states. The proposed DA is a run-time reconfigurable and lets system change the coefficients of FIR filter dynamically. The design was simulated, and the results were verified via two-phase power calculation method. The power calculations are based on forward synthesis invariant points and backward synthesis oriented activity approach. This method was applied to calculate the power and area of the proposed DA and other well-known counterparts in the literature. In the experimental results on 180 nm CMOS ASIC synthesis, the maximum clock of 100 MHz is achieved. In the 32-tap FIR filter implementation of our proposed DA and best known DA2 in serial DA structure, the switching power and internal power improvements are about 21 % and 10 %, respectively, in approximately equal speed and 5 % area increment.     

Design techniques for high-speed multirate multistage FIR digital filters

This paper presents architecture design techniques for implementing both single-rate and multirate high-speed finite impulse response (FIR) digital filters, with emphasis on the multirate multistage interpolated FIR (IFIR) digital filters. Well-known techniques to achieve high-speed and low-power applications for the single-rate digital FIR architecture are summarized, followed by the introduction of variable filter order selection, optimal filter decomposition, memory-saving and mirror symmetric filter pairs techniques which offer further gains in both performance and complexity reduction for the multirate multistage digital FIR architecture. A filter design example with TSMC 0.25?µm standard cell for 64-QAM baseband demodulator shows that the area is reduced by 39% for low-complexity application. Moreover, for high-speed application, the chip can operate at 714?MHz. Finally, a designed decimator which is used in the CDMA cellular shows that the area is reduced by 70% as compared with conventional approach.     

基于MATLAB及FPGA的高速FIR滤波器的设计

FIR滤波器是一种被广泛应用的基本的数字信号处理部件。现提出采用MATLAB的窗函数方法设计并在附上实现高速FIR滤波器的一种新的方案。这种结构采用流水线技术，通过对高速乘法器的合理分割并组合Wallace加法树阵列构成，可以方便地调整滤波器的阶数和系数，适合不同场合的应用。通过编程调试结果表明，该设计是可靠的，可作为高速数字滤波器设计的较好方案。     

Integrated mixed-mode digital-analog filter converters

Alternative architectures have been investigated for the integrated realization of DAFICs (digital-analog filter converters), taking into account such important design parameters as capacitance spread and total capacitor area, conversion speed and resolution, and the hardware complexity of the analog and digital parts. To demonstrate the feasibility of this novel building block, an experimental prototype algorithmic DAFIC with 8-b resolution and four FIR (finite impulse response) filtering coefficients was integrated using a 3-μm single-metal/double-poly CMOS process. Experimental results are shown to be in good agreement with the expected theoretical behavior. Preliminary work indicates that the DAFIC building block possesses significant practical advantages for the implementation of adaptive transversal structures required in baseband digital transmission applications with echo cancellation     

Bit-serial VLSI implementation of delayed LMS adaptive FIR filters

The delayed least-mean-square (DLMS) algorithm is useful for adaptive finite impulse response (FIR) filtering applications where high throughput rates are required. In the paper, a bit-serial bit-level systolic array based on new schemes for multiplication and inner-product computation is presented to implement DLMS adaptive N-tap FIR filters. The architecture is highly regular, modular, and thus well-suited to VLSI implementation. It has an efficiency of 100% and a throughput rate of one filter output per 2B cycles, where B is the word length of input data. In addition, the proposed array uses a small delay of [(4B+N/2+4)/2B] in the filter coefficient adaptation, where [x] is the smallest integer greater than or equal to x. This ensures that the DLMS algorithm can have good performance under proper selection of the step size. Based on a conservative design technique of static complementary metal oxide semiconductor (CMOS) logic, it is shown that the proposed system can be realized in a single chip for most practical applications     

An unbiased p-step predictive FIR filter for a class of noise-free discrete-time models with independently observed states

The paper addresses a new unbiased p-step toward predictive finite impulse response (FIR) filter for a class of discrete-time deterministic state space models, which states are represented on a horizon of N past points with degree polynomials and observed independently. It is implied that measurements are not available at a current time point n. The problem arises in synchronization and tracking when a signal is lost. Generic coefficients are derived via the Bernoulli polynomials for a two-parameter family of the polynomial filter gains. A generalization is provided for the linear (ramp) and quadratic filter gains. We show that the solution proposed is efficient in applications to predictive filtering of the states of local clocks of digital communication network nodes when a synchronizing signal is temporarily not available.     

Design of High-Order Extrapolated Impulse Response FIR Filters with Signed Powers-of-Two Coefficients

Expensive multiplication operations can be replaced by simpler additions and hardwired shifters so as to reduce power consumption and area size, if the coefficients of a digital filter are signed power-of-two (SPT). As a consequence, FIR digital filters with SPT coefficients have been widely studied in the last three decades. However, most approaches for the design of FIR filters with SPT coefficients focus on filters with length less than 100. These approaches are not suitable for the design of high-order filters because they require excessive computation time. In this paper, an approach for the design of high-order filters with SPT coefficients is proposed. It is a two-step approach. Firstly, the design of an extrapolated impulse response (EIR) filter is formulated as a standard second-order cone programming (SOCP) problem with an additional coefficient sensitivity constraint for optimizing its finite word-length effect. Secondly, the obtained continuous coefficients are quantized into SPT coefficients by recasting the filter-design problem into a weighted least squares (WLS) sequential quadratic programming relaxation (SQPR) problem. To further reduce implementation complexity, a graph-based common subexpression elimination (CSE) algorithm is utilized to extract common subexpressions between SPT coefficients. Simulation results show that the proposed method can effectively and efficiently design high-order SPT filters, including Hilbert transformers and half-band filters with SPT coefficients. Experiment results indicate that 0.81N∼0.29N adders are required for 18-bit N-order FIR filters (N=335∼3261) to meet the given magnitude response specifications.     

Efficient bit-level systolic array implementation of FIR and IIRdigital filters

Bit-level systolic architectures based on an inner-product computation scheme for finite-impulse response (FIR) and infinite-impulse-response (IIR) digital are presented. The FIR filter structure is optimized in the sense that for a given clock rate, both the utilization efficiency and average throughput are maximized. The IIR filter structure has approximately the same utilization efficiency and throughput rate as previous related techniques for processing a single data stream (channel), but it allows two data streams to be processed concurrently to double the performance. This feature makes the IIR system attractive for use in applications where multiple filtering and particularly bandpass analysis are required     

High-performance FIR filter design based on sharing multiplication

Finite impulse response (FIR) filtering can be expressed as multiplications of vectors by scalars. We present high-speed designs for FIR filters based on a computation sharing multiplier which specifically targets computation re-use in vector-scalar products. The performance of the proposed implementation is compared with implementations based on carry-save and Wallace tree multipliers in 0.35-/spl mu/m technology. We show that sharing multiplier scheme improves speed by approximately 52 and 33% with respect to the FIR filter implementations based on the carry-save multiplier and Wallace tree multiplier, respectively. In addition, sharing multiplier scheme has a relatively small power delay product than other multiplier schemes. Using voltage scaling, power consumption of the FIR filter based on computation sharing multiplier can be reduced to 41% of the FIR filter based on the Wallace tree multiplier for the same frequency of operation.