基于区域内存模型的空指针引用缺陷检测

为了实现对C程序中空指针引用的充分检测,本文提出了一种基于区域内存模型的空指针引用缺陷检测方法.首先,提出了基于区域的符号化三值逻辑（Region-based Symbolic Three-Valued Logic,RSTVL）,RSTVL能够描述C程序运行时内存中数据结构的形态信息与变量的存储状态,以及可寻址表达式间的各种关系;其次,给出了基于抽象语法树与函数摘要识别被引用指针方法;最后,结合基于RSTVL的数据流分析结果,将对被引用指针的检测转换为对相应区域的检测,给出了空指针引用缺陷检测的方法,通过函数摘要实现过程间的空指针引用缺陷检测.对比实验结果表明,本文方法在保证一定检测准确率的前提下,能够极大的减少空指针引用缺陷的漏报.     

多种语言混合编程技术（续）

2.2 Microsoft语言的内存模式2.2.1 什么是内存模式以及为什么要使用内存模式内存模式是计算机使用内存的方式,是在程序被编译时通过命令行参数(或缺省地)指定的,编译器根据指定的内存模式来组织程序的代码段和数据段.在不同的内存模式下,编译器产生的程序调用指令、子程序返回指令都会不同,在通过引用传递参量时,压入堆栈中的参量地址也会不同.因此,在进行混合语言编程时,使用的内存模式必须相互兼容.     

RMX86操作系统核心程序剖析

本文简要剖析了RMX86实时操作系统的核心程序,主要针对核心程序所涉及的数据结构,并概括地介绍核心程序本身的构造。核心程序操作的对象是目标,任务调度的主要数据结构是链表,本文首先就这两者作了较为详尽的阐述,然后,文章对内存管理与程序构造作了粗略的分析;最后,就几个主要的目标作了专题性讨论。这些内容为深入全面地分析核心程序提供了必要的基本素材。     

基于内存操作的动态软件水印算法

提出了一种基于内存操作的动态软件水印算法,算法通过控制本地代码程序中的内存分配释放和使用等行为隐藏软件水印。定义了动态簇、簇间内存关系、内存关系矩阵等概念,详细描述了软件水印的嵌入和提取过程。分析了算法的平台依赖性、可信性、数据率、开销,并通过实验对该算法的隐蔽性和抗攻击能力进行了探讨。     

内存数据库Redis在条件接收系统中的应用

Redis是一个作用于内存的数据结构存储系统,它可以作为数据库、缓存或者消息中间件,支持多种类型的数据结构.条件接收系统(Conditional Access System,CAS)是数字电视加密控制的核心付费数字电视的核心技术,是对数字电视内容的一种保护手段,保证用户只有在满足一定的条件下才能正常收看特定的内容.随着用户量的增长,条件接受系统对信息存储提出了更高的要求.目前系统提高性能的方法主要有存储虚拟化、存储内存化、多平台的互操作和数据共享等,因此条件接收系统采用加入内存数据库Redis这种新的存储技术来大幅度提高信息存储的速度.本文主要介绍Redis内存数据库的现状以及如何将Redis内存数据库与现有的条件接收系统相结合来提高条件接收系统性能.     

C/C++源代码静态检测系统的设计和实现

为了检测出C/C++源代码程序中常见的运行时错误,设计了一个静态检测系统。该系统通过词法分析、语法分析、语义分析来获取程序的语法树。然后系统的检测程序将会分析语法树的每一个结点,判断结点中的属性信息是否存在错误。创新点在于语法树数据结构和检测程序的设计。通过检测程序对结点的属性值的分析,能够检测出C/C++源代码程序中出现的数组越界、指针错误、字符串函数错误,内存泄露等问题。     

与异常相关的C++程序安全漏洞研究

分析了C++程序中与异常相关的安全漏洞,以及这些漏洞会引起内存泄漏、程序的控制流异常和数据流异常.根据几种常见安全漏洞的表现形式,结合实例详细分析了这些安全漏洞产生原因及特点,并给出安全编程的建议.     

TSR程序释放的研究

本文一改以往TSR程序动态释放的传统方法(即自身先驻留内存,成为一个TSR程序,然后对在其后进入内存的TSR程序进行释放),提出并编制了一个能自动对内存的TSR程序进行检测、释放而其本身不占任何内存的软件。     

面向对象程序设计刍议

面向对象程序设计是一种围绕真实世界的概念来组织模型的程序设计方法，对象是包含现实世界物体特征的抽象实体。在计算机科学中，程序操作的任何成分都可以看作一个对象，一个类所有的对象都有相同的数据结构，并且共享相同的操作代码，所以说类是所有对象共同的行为和不同状态的集合体。本文通过对电视机类的定义阐述了电视机的基本功能及工作原理，来说明类是创建对象的模块，一个类所有的对象都有相同的数据结构的概念。     

内存数据库的数据结构分析

数据库管理系统获得高性能的一个方法就是将数据库存放在内存中而不是存放在磁盘上 ,这样就必须设计出一种新的数据结构和算法来更有效地利用 CPU周期和内存空间。本文介绍了几种适合于内存数据库的物理数据组织方法和当前内存数据库管理系统的几种索引结构     

Novel Approach to Minimize the Memory Requirements of Frequent Subgraph Mining Techniques

Frequent subgraph mining (FSM) is a subset of the graph mining domain that is extensively used for graph classification and clustering. Over the past decade, many efficient FSM algorithms have been devel-oped with improvements generally focused on reducing the time complexity by changing the algorithm structure or using parallel programming techniques. FSM algorithms also require high memory consumption, which is another problem that should be solved. In this paper, we propose a new approach called Predictive dynamic sized structure packing (PDSSP) to minimize the memory needs of FSM algorithms. Our approach redesigns the internal data structures of FSM algorithms without making algorithmic modifications. PDSSP offers two contributions. The first is the Dynamic Sized Integer Type, a newly designed unsigned integer data type, and the second is a data structure packing technique to change the behavior of the compiler. We examined the effectiveness and efficiency of the PDSSP approach by experimentally embedding it into two state-of-the-art algorithms, gSpan and Gaston. We compared our implementations to the performance of the originals. Nearly all results show that our proposed implementation consumes less memory at each support level, suggesting that PDSSP extensions could save memory, with peak memory usage decreasing up to 38％depending on the dataset.     

一种基于深度学习的强对抗性Android恶意代码检测方法

针对现有Android恶意代码检测方法容易被绕过的问题,提出了一种强对抗性的Android恶意代码检测方法.首先设计实现了动静态分析相结合的移动应用行为分析方法,该方法能够破除多种反分析技术的干扰,稳定可靠地提取移动应用的权限信息、防护信息和行为信息.然后,从上述信息中提取出能够抵御模拟攻击的能力特征和行为特征,并利用一个基于长短时记忆网络（Long Short-Term Memory,LSTM）的神经网络模型实现恶意代码检测.最后通过实验证明了本文所提出方法的可靠性和先进性.     

Efficient co-simulation framework enhancing system-level power estimation for a platform-based SoC design

This paper proposes a hardware–software (HW-SW) co-simulation framework that provides a unified system-level power estimation platform for analyzing efficiently both the total power consumption of the target SoC and the power profiles of its individual components. The proposed approach employs the trace-based technique that reflects the real-time behavior of the target SoC by applying various operation scenarios to the high-level model of target SoC. The trace data together with corresponding look-up table (LUT) is utilized for the power analysis. The trace data is also used to reduce the number of input vectors required to analyze the power consumption of large H/W designs through the trade-offs between the signal probability in the trace results and its effect on the power consumption. The effect of cache miss on power, occurring in the S/W program execution, is also considered in the proposed framework. The performance of the proposed approach was evaluated through the case study using the SoC design example of IEEE 802.11a wireless LAN modem. The case study illustrated that, by providing fast and accurate power analysis results, the proposed approach can enable SoC designers to manage the power consumption effectively through the reconstruction of the target SoC. The proposed framework maps all hardware IPs into FPGA. The trace based approach gets input vectors at transactor of the each IP and gets power consumption indexing a LUT. This hardware oriented technique reports the power estimation result faster than the conventional ones doing it at S/W level.     

曲面共形阵列结构快速数值分析方法

针对曲面共形阵列结构电磁散射特性的高效、精确仿真分析需求,提出了一种并行综合函数矩量法处理方案.该方法是传统电磁经典数值算法——矩量法的一种改进形式,通过几何区域分解处理和综合基函数的方式极大降低了算法的内存消耗,使得单机分析电大尺寸问题和大规模阵列问题成为可能.更为重要的是,针对周期阵列结构,该方法具备综合函数复用特性和多区域并行处理特性,能够大大提高算法的综合处理效率.一个6×11的柱面共形贴片阵列被用于验证所提方法的性能,仿真结果表明,对于周期阵列结构,该方法的计算精度与多层快速多极子算法相当,虽然计算效率略低于多层快速多极子方法,但内存消耗比多层快速多极子方法低一个数量级.     

Condensed recursive structures for computing multidimensional DCT/IDCT with arbitrary length

In this paper, efficient recursive structures for computing arbitrary length M-dimensional (M-D) discrete cosine transform (DCT) and its inverse DCT (IDCT) are proposed. The M-D DCT and IDCT are first converted into condensed one-dimensional (1-D) DCT and discrete sine transform (DST) with a regular preprocessing procedure. The recursive filters for condensed 1-D DCT/DST are then derived by using Chebyshev polynomials to compute M-D DCT/IDCT without data transposition. The proposed structures require fewer recursive loops than traditional 1-D recursive structures, which are realized in M passes and (M-1) data transposition by the so-called row-column approach. With advantages of fewer recursive loops and no transposition memory, the proposed structures attain more accurate results and less power consumption than traditional row-column structures. The proposed recursive M-D DCT/IDCT structures are suitable for very large-scale integration implementation due to regular and modular features.     

Signal Assignment Model for the Memory Management of Multidimensional Signal Processing Applications

Many signal processing systems, particularly in the multimedia and telecom domains, are synthesized to execute data-dominated applications. Their behavior is described in a high-level programming language, where the code is typically organized in sequences of loop nests and the main data structures are multidimensional arrays. Since data transfer and storage have a significant impact on both the system performance and the major cost parameters—power consumption and chip area, the designer must spend a significant effort during the system development process on the exploration of the memory subsystem in order to achieve a cost-optimized design. This paper presents a memory allocation methodology for multidimensional signal processing applications, focusing on the problem of efficiently mapping the multidimensional signals from the algorithmic specification into the physical memory. In a first phase, two previous mapping models are implemented within a common theoretical framework, which is advantageous from both the point of view of computational efficiency and the amount of allocated data storage. Different from all the previous mapping models that aim to optimize the memory sharing between the elements of a same array (creating separate windows in the physical memory for distinct arrays), this proposed mapping model exploit—in a second phase—the possibility of memory sharing between the elements of different arrays. As a consequence, this signal assignment approach yields significant savings in the amount of data storage resulted after mapping.     

一种基于并行Bloom Filter的高速URL查找算法

URL查找是众多网络系统中重要的组成部分,如URL过滤系统、Web缓存等.随着互联网的迅速发展,URL查找面临的主要挑战是实现大规模URL集合下的高速查找,同时保证低存储和低功耗.本文提出了一种基于并行Bloom Filter的URL查找算法,CaBF.该算法高度并行化,提供大规模URL集合下的高速最长前缀匹配,并很好地适应集合中不同数量的URL组件.理论分析和真实网络数据集上的实验表明,该算法相比现有算法可以降低假阳性概率达一个数量级(或者在满足相同假阳性概率的前提下降低存储和硬件逻辑资源消耗).此外,该方法的体系结构很容易映射到FPGA等硬件器件上,提供每秒超过150M次的URL查找速度.     

基于虚拟机自省的运行时内存泄漏检测模型

云计算及数据中心领域中已广泛采用虚拟化技术来尽可能消除虚拟计算环境中的内存泄漏是提高其可靠性的一种重要途径。提出了一种基于虚拟机自省机制的运行时内存泄漏的信息流检测模型与内存泄漏的判定方法,设计并实现了该模型的原型系统。通过对原型系统的有效性与性能评估实验分析,结果表明,该模型方法能有效地检测出运行时内存泄漏,并且具有较好的性能。     

A novel approach of tensor‐based data missing estimation for Internet of Vehicles

In the face of the current huge amount of intelligent traffic data, collecting and statistical processing is a necessary and important process. But the inevitable data missing problem is the current research focus. In this paper, a novel approach of tensor‐based data missing estimation for Internet of Vehicles is proposed for the problem of missing the Internet of Vehicles data: Integrated Bayesian tensor decomposition (IBTD). In the data model construction stage, the random sampling principle is used to randomly extract the missing data to generate a subset of data. And the optimized Bayesian tensor decomposition algorithm is used for interpolation. Introduce the integration idea, analyze, and sort the error results after multiple interpolations, consider the space‐time complexity, and choose the optimal average to get the best result. The performance of the proposed model was evaluated by mean absolute percentage error (MAPE) and root mean square error (RMSE). The experimental results show that the proposed method can effectively interpolate the traffic data sets with different missing quantities and get good interpolation results.     

Incremental analysis of large VLSI Layouts

The verification of VLSI layouts is an important and expensive step in physical design process and has significant contribution in overall design cycle time. Design rule checking, connectivity extraction and device extraction are important steps in layout analysis. Efficient incremental algorithms for these steps are crucial for fast development as well as small time-to-market of the design. If the size of layout is so large that it cannot fit entirely into available main memory, the main performance bottleneck is communication between internal memory and the external memory due to the slow access speed of external memory.In this paper, incremental solutions for problems of layout analysis are presented considering the external memory management. The main component of these algorithms is the proposed “recursive tiling” approach, which provides an easy to implement data structure for the aggregation of parts of layout for fast search and updates. Experimental results show that the recursive tiling approach proposed in this paper has reduced the time required for incremental processing on the workstations with limited amount of physical memory.