An analytical model for punch-through limited breakdown voltage of planar junction with multiple floating field limiting rings

An appropriate model for punch-through (PT) limited breakdown voltage of a planar junction is presented for the first time as a function of the normalized epitaxial layer thickness and the critical depletion width of the cylindrical junction at breakdown in non-PT case. The results are applied to the planar junction structure with a single ring, taking into account three different breakdown modes. The problem of the multiple ring structure is solved using the equivalent ring method, which allows determination of the PT limited breakdown voltage and optimized ring spacings for the structure. Comparisons with two-dimensional device simulations using MEDICI show a good agreement.     

Increased junction breakdown voltages in silicon-on-insulatordiodes

A junction breakdown model and the results of PISCES II simulations are presented for silicon-on-insulator (SOI) devices. This model shows the dependence of breakdown voltage in fully depleted (FD) SOI diode on the backgate bias, the properties of the buried oxide layer, and the device parameters. Breakdown in a thin FD SOI diode is quite different from that observed in a thicker, partially depleted (PD) diode. The analysis is supported by breakdown voltage measurements of separation by implantation of oxygen (SIMOX)-based SOI diodes, the results of which suggest that body breakdown is dominant in FD SOI diodes, and the junction curvature effect is dominant in PD SOI diodes. Furthermore, the results also show that breakdown voltage in the FD SOI diode is higher than their bulk-silicon counterpart and can be further increased by applying the appropriate backgate bias     

Analytical solutions for the breakdown voltages of punched-through diodes having curved junction boundaries at the edges

Analytical expressions are derived for the breakdown voltages of punched-through diodes having a plane structure terminated with cylindrical and spherical curved boundaries at the edges, through the use of suitable approximations for the electric field in the depletion layer. The expressions derived include both p⁺-i-n⁺and p⁺-p-n⁺(or p⁺-n-n⁺) types and are given in terms of the middle-region (i-layer or p-layer) width, the radius of curvature of the junction edge, the punch-through voltage, and the plane parallel breakdown voltage of p⁺-i-n⁺diodes. The results obtained include a correlation between the middle-region (p-layer) width and the width of the depletion layer in the curved portions of the junction when the applied reverse bias across the diode is just sufficient so that punchthrough takes in the portions where the junction is plane parallel. These results are made use of in the breakdown voltage calculations.     

Schottky base edge leakage in Si permeable-base transistors

The base leakage/breakdown mechanism in the Si permeable-base transistor (SiPBT) is related to the radius of curvature of the depletion region directly below the edge of the metal semiconductor interface. The unique geometry of the SiPBT illustrates the edge breakdown phenomena. As higher reverse bias is applied to the base-collector junction, the adjacent depletion regions in the grating fuse and the exposed edge perimeter will vary to form a kink in the IV characteristics. The grating will self-guard. As the SiPBT design parameters are scaled to finer gratings, the carrier concentration under the base must increase to maintain permeable-base transistor action. These fine-period SiPBT's will also self-guard within the grating region.     

Breakdown walkout in planar p-n junctions

Junction breakdown walkout in p-n junctions has been investigated in this paper. It has been shown that walkout is closely related to the avalanching in the junction. During the time the junction is subjected to the reverse breakdown, because of avalanching, hot electrons are generated in the depletion region. Some of the hot electrons have enough energy to cross the oxide-silicon barrier and to go into the conduction band of the oxide. The electrons are trapped in the traps and charge the oxide negatively, resulting in reduction of electric field intensity in the surface depletion region of the p-n junction. This results in an increase of the breakdown voltage. A theory has been developed to explain hot electron injection and trapping in the oxide and its effect on the breakdown voltage. A comparison of results predicted by theory, with the experiments has also been carried out.     

Self-aligned shallow junction MJFET (metal junction FET) for higherturn-on and breakdown voltages

Simple self-aligned p⁺⁺-gate formation technology for a junction field-effect transistor (JFET) using elemental shallow Zn diffusion from patterned Au/Zn gate metal is reported. This diffusion technology makes it possible to control a very shallow p⁺⁺-layer less than 50 nm. The metal junction FET (MJFET) shows about 0.3 V higher gate turn-on voltage in forward bias and much larger reverse breakdown voltage than the conventional Al-gate MESFET with similar transconductances, typically 200 mS/mm for 1.5-μm gate length quasi-enhancement, and 90 mS/mm for 4-μm gate length deep depletion devices     

Junction capacitance and related characteristics using graded impurity semiconductors

The transition capacitance of a junction of semiconductors with constant impurity density is well-known and varies inversely with the square root of the bias voltage. This paper analyzes the variation of transition capacitance with bias voltage of a junction of semiconductors with graded impurity densities; i. e., densities which are an arbitrary function of position. It is found that the transition capacitance can be simply related to a depletion width and that, in turn, depletion width can be related to the bias voltage. An analysis is also carried out for the impurity grading to produce a specified transition capacitance variation, as for instance, a linear variation of capacitance with bias voltage. It is also possible to determine impurity gradings to satisfy certain special conditions. An example of this type that is considered in some detail is the determination of the impurity grading which will produce avalanche breakdown simultaneously throughout the semiconductor. An important result of the analysis is that the capacitance vs bias voltage relation can be favorably modified by suitable choice of impurity grading (see Fig. 7). The practical realization of the various characteristics considered in this article is contingent upon techniques for fabricating semiconductors with specified impurity gradings.     

Evaluation of voltage dependent series resistance of epitaxial varactor diodes at microwave frequencies

The series resistance of a high-quality varactor diode is primarily determined by the resistance of the semiconductor material close to the junction. With increasing reverse bias, the width of the space-charge region becomes greater, and the series resistance decreases. Theoretical models of graded and step junctions have been assumed, and calculations have been made of the series resistance as a function of bias. Epitaxial silicon diodes have been measured for series resistance as a function of bias by using the transmission loss method at 6 to 12 Gc/s, with the diode mounted across a reduced-height waveguide. The variation of series resistance with bias agrees well with the theoretical calculations. By measuring of the 3-dB bandwidth of the series resonance of the diode mounted in the reduced-height waveguide, the junction capacitance and the effective series inductance of the package also can be determined. Because the width of the space-charge region must vary with applied voltage in order to obtain the varactor characteristic, the diode cannot have zero-series resistance at zero-volt bias. The minimum possible series resistance is a function of the breakdown voltage and increases with increasing breakdown voltage. Calculations of the maximum possible cutoff frequency as a function of the diode breakdown voltage are presented for both graded and step junction silicon varactors. A plot of series resistance vs. reverse bias can be used to determine the impurity concentration profile in the epitaxial film. The impurity concentration profile can also be determined by measuring the capacitance vs. reverse bias, a technique which has been in use for some time. However the former method appears to be more accurate in that it is independent of junction area.     

Unlimited High Breakdown Voltage by Natural Super Junction of Polarized Semiconductor

A breakdown mechanism of polarized semiconductors represented by GaN-based materials is presented, based on the concept of a natural super junction, which is established by the inherent material polarization. In this concept, owing to the precise matching of positive and negative polarizations of both sides of GaN and AlGaN materials, average charge concentration in the material becomes nearly zero under reverse bias condition, which realizes extremely high breakdown voltage. This model is confirmed by device simulation taking all polarization charges of GaN-based materials into account. Furthermore, experimentally fabricated GaN-based Schottky barrier diodes showed a linear increase of breakdown voltage along the anode-cathode spacing, achieving a record breakdown voltage over 9000 V.     

Electrical breakdown and recovery in rectifying m | lb | m structures

Metal 1 | C₁₆H₃₃–Q3CNQ LB film | metal 2 structures exhibiting asymmetric, non-linear I/V characteristics have been fabricated using the Langmuir–Blodgett (LB) technique with LB film thicknesses as small as a single monolayer. When such junctions are subjected to low biases, the I/V traces exhibit little or no asymmetry, but as the applied biases increase, so the I/V asymmetry becomes more evident. The largest applied voltages before breakdown are of the order of 1 V, which represents an E-field of order 10⁸ V m^?1. This breakdown under high biases increases the junction conductance and the I/V traces become very noisy. More interestingly, it has been observed that after such breakdown it is possible for the junction to recover on reduction of the bias. It is observed that recovery is not always immediate and may require several voltage sweeps. A subsequent increase in bias will cause breakdown at the same bias as the first breakdown, indicating that no permanent damage has been caused.     

An accurate and analytic threshold-voltage model for small-geometry MOSFETs with single-channel ion implantation in VLSI

This paper presents an accurate and analytic threshold-voltage model for n-channel enhancement MOSFETs with single-channel boron implantation. In the developed model, the step-profile approximation is used to simulate the channel-implanted profile and an accurate inversion condition is used to calculate the surface potential. Moreover, the built-in voltage across the step junction is taken into consideration, which insures the continuities of surface potential and maximum depletion width changes with respect to the applied substrate bias as the edge of maximum depletion width passes through the step junction. A modified charge-sharing model is also developed to consider the charge-sharing effect due to source and drain diffusion islands and is incorporated into the developed threshold-voltage model by the depletion-charge-superposition method. In addition, the charge-sharing effect due to the bird's beak and field-encroachment implant has also been considered in the developed model. The experimental devices fabricated by a set of test keys have been characterized. The measured threshold voltages are compared to the developed model and excellent agreement between comparisons has been obtained for wide ranges of channel lengths, channel widths, and applied substrate biases. Moreover, a method of extracting the implant parameters for a step profile and the flatband voltage is also presented.     

Visible light emission from silicon MOSFETS

We observe visible light emission from Si MOSFET beyond source-drain breakdown. The intensity as well as location varies with gate bias. For zero gate-voltage (V_g) light is seen from four sides of the drain region. But for positive V_g values the location of the light emission shifts to the drain-gate boundary and has a peak in emission intensity at a certain gate bias beyond which it decreases. The initial increase in light intensity is attributed to minority-carrier injection and the decrease at higher gate bias is due to a reduction of lateral field beyond pinch off, which causes a decrease in carrier multiplication. For negative gate-bias, the source-drain breakdown voltage decreases and hence the light intensity increases. A theoretical model for the drain current beyond breakdown is presented and compared with experimental light-intensity curves. The substrate current, which is a measure of the avalanche mechanism by an electron-hole pair generation in the drain depletion region, is measured and compared with light-intensity values.     

Super Junction LDMOS Transistors - Implementing super junction LDMOS transistors to overcome substrate depletion effects

The super junction (SJ) concept (Coe et al.) applied to power semiconductor devices is attractive due to its potential for reducing on-resistance at a given breakdown voltage. Discrete SJ vertical power devices have recently become available commercially. However, lateral SJ devices have not materialized for several years partly due to the fact that the lateral SJ structure, implemented on silicon substrates, suffers from substrate-assisted depletion effects which reduce the breakdown voltage. This article discusses the various device structures that have been proposed to eliminate the substrate-assisted depletion effects in SJ-lateral double diffused MOS LDMOS transistors (SJ-LDMOSTs). The concept of the SJ device and vertical and lateral SJ structure was summarized. The substrate-assisted depletion effects are described in detail. The alternative implementations proposed to suppress the substrate effects were then discussed. And the experimental implementation results are summarized and discussed to identify the most likely option for the implementation of lateral SJ-LDMOSTs     

InGaN/GaN MQW p–n junction photodetectors

InGaN/GaN multiquantum well (MQW) p–n junction photodetectors with semi-transparent Ni/Au electrodes were fabricated and characterized. It was found that the fabricated InGaN/GaN MQW p–n junction photodetectors exhibit a 20 V breakdown voltage and a 3.5 V forward 20 mA turn on voltage. It was also found that the photocurrent to dark current contrast ratio is higher than 10⁵ when a 0.4 V reverse bias was applied to the InGaN/GaN MQW p–n junction photodetectors. Furthermore, it was found that the maximum responsivity was 1.28 and 1.76 A/W with a 0.1 and 3 V applied reverse bias, respectively.     

Analysis of dielectric breakdown in CoFeB/MgO/CoFeB magnetic tunnel junction

The time-dependent dielectric breakdown has been investigated in a series of nominally identical Co–Fe–B/MgO/Co–Fe–B junctions by voltage ramp experiments. The results divulge that the breakdown voltage strongly depends on the polarity of the applied voltage, junction area, ramp speed and the annealing temperature. Magnetic tunnel junctions (MTJs) with positive bias on the top electrode show higher breakdown voltage than MTJs with negative bias. We found that there is a significant decrease in the breakdown voltage when the annealing temperature is increased above 350 °C. The experimental data can be described by different specific forms of breakdown probability functions which lead to different extrapolation of life time of junctions.     

Proposed method for controlling and minimizing reflections from a surface

This paper proposes a method whereby the reflection of an electromagnetic wave from a surface can be controlled. The idea is to use a p-n junction as the controlling device. The device is made in such a way that the junction is parallel to the surface upon which the electromagnetic radiation is impinging. If the p region is very narrow the wave will penetrate through it into the depletion region. If the n region is hi conductivity, the wave is reflected from it. Then if the depletion layer width is right for the frequency considered, the reflected wave will interact with the impinging wave to give the desired effect. By changing the bias applied to the junction a tuning effect can be obtained. Detailed analysis of the proposed device is covered in the paper. There are some practical limitations to creating the device described, but the idea and the method of analysis could be useful to individuals interested in creating microwave tuning and control components.     

A numerical model of avalanche breakdown in MOSFET's

An accurate numerical model of avalanche breakdown in MOSFET's is presented. Features of this model are a) use of an accurate electric-field distribution calculated by a two-dimensional numerical analysis, b) introduction of multiplication factors for a high-field path and the channel current path, and c) incorporation of the feedback effect of the excess substrate current induced by impact ionization into the two-dimensional calculation. This model is applied to normal breakdown observed in p-MOSFET's and to negative-resistance breakdown (snap-back or switchback breakdown) observed in short-channel n-MOSFET's. Excess substrate current generated from channel current by impact ionization causes a significant voltage drop across the substrate resistance in short-channel n-MOSFET's. This voltage forward-biases the source-substrate junction and increases channel current causing a positive feedback effect. This results in a decrease of the breakdown voltage and leads to negative-resistance characteristics. Current-voltage characteristics calculated by the present model agree very well with experimental results. Another model, highly simplified and convenient for device design, is also presented. It predicts some advantages of p-MOSFET's over n-MOSFET's from the standpoint of avalanche breakdown voltage, particularly in the submicrometer channel-length range.     

由等价掺杂转换理论得到非对称线性缓变P-N结的击穿特性

基于等价掺杂转换理论的应用,得到了解析计算非对称线性缓变P-N结击穿特性.由于非对称线性缓变P-N结是单扩散P-N结的一个恰当近似,因而,研究其击穿特性可以更好地理解和设计功率器件P-N结的终端结构.运用等价掺杂转换方法的基本理论得到了不同扩散掺杂梯度和衬底浓度组合系列的击穿电压.研究了最大耗尽层宽度在扩散侧和衬底侧的扩展,给出了它们随扩散掺杂梯度和衬底浓度组合的变化而出现的不同特点.本方法预言的最大击穿电压较之单纯的突变结和对称线性缓变P-N结更接近文献报道的结果,显示了等价掺杂转换理论的理论计算非对称线性缓变P-N结击穿电压的有效性.     

由等价掺杂转换理论得到非对称线性缓变P-N结的击穿特性

基于等价掺杂转换理论的应用,得到了解析计算非对称线性缓变P-N结击穿特性.由于非对称线性缓变P-N结是单扩散P-N结的一个恰当近似,因而,研究其击穿特性可以更好地理解和设计功率器件P-N结的终端结构.运用等价掺杂转换方法的基本理论得到了不同扩散掺杂梯度和衬底浓度组合系列的击穿电压.研究了最大耗尽层宽度在扩散侧和衬底侧的扩展,给出了它们随扩散掺杂梯度和衬底浓度组合的变化而出现的不同特点.本方法预言的最大击穿电压较之单纯的突变结和对称线性缓变P-N结更接近文献报道的结果,显示了等价掺杂转换理论的理论计算非对称线性缓变P-N结击穿电压的有效性.