Sub-1 V,pico-watt subthreshold CMOS voltage reference circuit with dual temperature compensation

A pico-watt CMOS voltage reference is developed using an SK Hynix 0.18 µm CMOS process. The proposed architecture is resistorless and consists of MOSFET circuits operated in the subthreshold region. A dual temperature compensation technique is utilized to produce a near-zero temperature coefficient reference output voltage. Experimental results demonstrate an average reference voltage of 250.7 mV, with a temperature coefficient as low as 3.2 ppm/°C for 0 to 125 °C range, while the power consumption is 545 pW under a 420 mV power supply at 27 °C. The power supply rejection ratio and output noise without any filtering capacitor at 100 Hz are −54.5 dB and 2.88 µV/Hz^1/2, respectively. The active area of the fabricated chip is 0.00332 mm².     

Power cycle reliability of Cu nanoparticle joints with mismatched coefficients of thermal expansion

The power cycle reliability of Cu nanoparticle joints between Al₂O₃ heater chips and different heat sinks (Cu-40 wt.%Mo, Al-45 wt.%SiC and pure Cu) was studied to explore the effect of varying the mismatch in the coefficient of thermal expansion (CTE) between the heater chip and the heat sink from 4.9 to 10.3 ppm/K. These joints were prepared under a hydrogen atmosphere by thermal treatment at 250, 300 and 350 °C using a pressure of 1 MPa, and all remained intact after 3000 cycles of 65/200 °C and 65/250 °C when the CTE mismatch was less than 7.3 ppm/K, despite vertical cracks forming in the sintered Cu. When the CTE mismatch was 10.3 ppm/K, the Cu nanoparticle joint created at 300 °C endured the power cycle tests, but the joint created at 250 °C broke by lateral cracks in the sintered Cu after 1000 cycles of 65/200 °C. The Cu nanoparticle joint created at 350 °C also broke by vertical cracks in the heater chip after 1000 cycles of 65/250 °C, suggesting that although sintered Cu can be strengthened to tolerate the stress by increasing the joint temperature, this eventually causes the weak and brittle chip to fracture through accumulated stress. The calculation results of stresses on the heater chip showed that the stress can be higher than the strength of Al₂O₃ when the CTE mismatch is 10.3 ppm/K and the Young's modulus of the sintered Cu is higher than 20 GPa, suggesting that the heater chip can be broken.     

A 1.58 nW power consumption and 34.45 ppm/°C temperature coefficient bandgap reference (BGR) for subblocks of RFID tag

In this paper a bandgap reference (BGR) circuit irrespective of the temperature and the supply voltage variation with very low power consumption is proposed. The proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) generators of the proposed BGR, which has four cores cascaded with each other, are used in order to increase not only the output voltage, but also the output control ability for the temperature and the voltage insensitivity. To combine produced voltage from PTAT and CTAT generator, a weight combination circuit, which uses internal capacitors of transistors, is applied. Due to the fact that all of the transistors in such a topology are worked in sub-threshold region, the power consumption is significantly diminished to 1.58 nW. Also the variation of the temperature from −25 °C to 150 °C, leads to the temperature coefficient about 34.45 ppm/°C. The design simulation is done at 960 MHz frequency in TSMC 0.18 µm CMOS technology with the help of Cadence software. Also the post layout simulation result and the layout of the proposed circuit are presented. The output and the chip area of this BGR are 141.5 mV and 1387 µm² respectively.     

Design and implementation of micro-power temperature to duty cycle converter using differential temperature sensing

The CMOS based temperature detection circuit has been developed in a standard 180 nm CMOS technology. The proposed temperature sensor senses the temperature in terms of the duty cycle in the temperature range of −30 °C to +70 °C. The circuit is divided into three parts, the sensor core, the subtractor and the pulse width modulator. The sensor core consists of two individual circuits which generates voltages proportional (PTAT) and complementary (CTAT) to the absolute temperature. The mean temperature inaccuracy (°C) of PTAT generator is −0.15 °C to +0.35 °C. Similarly, CTAT generator has mean temperature accuracy of ±1 °C. To increase thermal responsivity, the CTAT voltage is subtracted from the PTAT voltage. The resultant voltage has the thermal responsivity of 6.18 mV/°C with the temperature inaccuracy of ±1.3 °C. A simple pulse width modulator (PWM) has been used to express the temperature in terms of the duty cycle. The measured temperature inaccuracy in the duty cycle is less than ±1.5 °C obtained after performing a single point calibration. The operating voltage of the proposed architecture is 1.80±10% V, with the maximum power consumption of 7.2 μW.     

A new type of low power read circuit in EEPROM for UHF RFID

A novel low power read circuit without reference in 1 k-bits electrically erasable and programmable (EEPROM) for UHF RFID is designed and implemented in SMIC 0.18 μm EEPROM process. The read power consumption is optimized using a pre-charge sense amplifier. To improve the performance of the read circuit, a self-detect circuit, a read control logic and a feedback scheme are adopted, combined with a special time sequence. For a power supply voltage of 1 V, an average power consumption of 1.6 μA for the read operation of the EEPROM can be achieved when the read clock frequency is 640 kHz. What is more, with a 110 °C temperature change, the read power consumption variation is as low as 12%. The die size of the EEPROM is 0.15 mm², where the read circuit occupies 0.0125 mm².     

CMOS temperature sensor with ring oscillator for mobile DRAM self-refresh control

This paper presents novel low-cost CMOS temperature sensor for controlling the self-refresh period of a mobile DRAM. In the proposed temperature sensor, the temperature dependency of poly resistance is used to generate a temperature-dependent bias current, and a ring oscillator driven by this bias current is employed to obtain the digital code pertaining to on-chip temperature. This method is highly area-efficient, simple and easy for IC implementation as compared to traditional temperature sensors based on bandgap reference. The proposed CMOS temperature sensor was fabricated with an 80 nm 3-metal DRAM process, which occupies extremely small silicon area of only about 0.016 mm² with under 1 μW power consumption for providing 0.7 °C effective resolution at 1 sample/s processing rate. This result indicates that as much as 73% area reduction was obtained with improved resolution as compared to the conventional temperature sensor in mobile DRAM.     

Inverter circuits on glass substrates based on ZnO-nanoparticle thin-film transistors

The integration technique and the properties of inverter circuits on glass substrates using ZnO nanoparticles as semiconductor material are presented. The inverter device consists of a switching and a load metal–insulator–semiconductor field-effect transistor with poly(4-vinylphenol) as the gate dielectric. Although the semiconductor is deposited by spin-coating of a colloidal ZnO dispersion and the process temperature is limited to 200 °C, the inverters show reasonable maximum peak gains at low power consumption. The maximum peak gain was 6 V/V, whereas the maximum static power dissipation density was less than 26 nW/μm². Additionally, the influence of the geometry ratio as well as of the supply voltage on the device performance has been investigated. With regard to the optical characteristics, the proposed technique leads to circuits with an optical transmittance of up to 80%.     

Dependence of the optoelectronic properties of selenium-hyperdoped silicon on the annealing temperature

Selenium-hyperdoped silicon was prepared by ion implantation at 100 eV to a dose of 6×10¹⁵ Se/cm², followed by furnace annealing at 500–900 °C for 30 min. A phase transition from amorphous to crystalline was observed for the sample annealed at 600 °C. Carrier density in the Se doping layer gradually increases with the annealing temperature and a high carrier/donor ratio of 7.5% was obtained at 900 °C. The effects of annealing temperature on the rectifying behavior and external quantum efficiency of n⁺p junctions formed on Se-hyperdoped silicon were also investigated. We found that 700 °C was the optimal annealing temperature for improving the crystallinity, below-bandgap absorption, junction rectification and external quantum efficiency of Se-doped samples.     

U- and L-shaped heat pipes heat sinks for cooling electronic components employed a least square smoothing method

Heat pipes-heat sink modules transfer heat from a heat source to the heat pipes, and then to the heat sink and out into the surrounding ambient, and are suitable for cooling electronic components through a forced convection mechanism. The configuration and thermal performance of the heat sinks with inserted heat pipes were studied in the present paper. This article uses experimental procedures to investigate the thermal performance of two embedded U-shaped heat pipe and six embedded L-shaped heat pipe thermal modules with different fan speeds and heat source areas. And via the superposition method and least-square estimators in experimental data, the performance curves of individual U- and L-shaped heat pipes were derived and predicted. Results show that the lowest thermal resistances of U- and L-shaped heat pipe-heat sinks are respectively 0.246 °C/W and 0.166 °C/W given dual fans operating at 3000RPM and 30 × 30 mm² heat sources. Results for a single U-shaped heat pipe are 0.04 °C/W at 78.85 W, while sequential results for L-shaped heat pipes are 1.04 °C/W, 2.07 °C/W, 2.76 °C/W, 2.19 °C/W and 1.7 °C/W between 34 W and 40 W.     

Empirical prediction model for Li/SOCl2 cells based on the accelerated degradation test

The empirical prediction model of residual capacity (Cap) for D-size Li/SOCl₂ cells has been developed and validated based on the accelerated degradation test (ADT) data. In this experiment, a series of constant storage temperatures (25 °C, 55 °C, 70 °C, and 85 °C) was selected and the residual capacity of each cell was monitored continuously during the aging test. The model was established by fitting twice. Firstly, time dependence of Cap (t, T) was investigated. Secondly, the generalized model of residual capacity was built. The prediction model, as a function of storage time and temperature, can precisely predict the value of residual capacity. The generalized empirical model of Cap, involving two aging processes, is valid for the degradation condition of temperatures from 25 °C to 70 °C. The first aging process completed rapidly within 7 days. The second aging process was accelerated by temperature with time^1/2 kinetics. For the cells stored at 85 °C, another failure mechanism may exist based on the departure of linear fitting coefficients.     

High thermal annealing effect on structural and optical properties of ZnO–SiO2 nanocomposite

The effect of annealing temperature on photoluminescence (PL) of ZnO–SiO₂ nanocomposite was investigated. The ZnO–SiO₂ nanocomposite was annealed at different temperatures from 600 °C to 1000 °C with a step of 100 °C. High Resolution Transmission Electron Microscope (HR-TEM) pictures showed ZnO nanoparticles of 5 nm are capped with amorphous SiO₂ matrix. Field Emission Scanning Electron Microscope (FE-SEM) pictures showed that samples exhibit spherical morphology up to 800 °C and dumbbell morphology above 800 °C. The absorption spectrum of ZnO–SiO₂ nanocomposite suffers a blue-shift from 369 nm to 365 nm with increase of temperature from 800 °C to 1000 °C. The PL spectrum of ZnO–SiO₂ nanocomposite exhibited an UV emission positioned at 396 nm. The UV emission intensity increased as the temperature increased from 600 °C to 700 °C and then decreased for samples annealed at and above 800^°C. The XRD results showed that formation of willemite phase starts at 800 °C and pure willemite phase formed at 1000 °C. The decrease of the intensity of 396 nm emission peak at 900 °C and 1000 °C is due to the collapse of the ZnO hexagonal structure. This is due to the dominant diffusion of Zn into SiO₂ at these temperatures. At 1000 °C, an emission peak at 388 nm is observed in addition to UV emission of ZnO at 396 nm and is believed to be originated from the willemite.     

Design,development and reliability testing of a low power bridge-type micromachined hotplate

In this paper, the development and reliability of a platinum-based microheater with low power consumption are demonstrated. The microheater is fabricated on a thin SiO₂ bridge-type suspended membrane supported by four arms. The structure consists of a 0.6 μm-thick SiO₂ membrane of size 50 μm × 50 μm over which a platinum resistor is laid out. The simulation of the structure was carried out using MEMS-CAD Tool COVENTORWARE. The platinum resistor of 31.0 Ω is fabricated on SiO₂ membrane using lift-off technique. The bulk micromachining technique is used to create the suspended SiO₂ membrane. The temperature coefficient of resistance (TCR) of platinum used for temperature estimation of the hotplate is measured and found to be 2.2 × 10⁻³/°C. The test results indicate that the microhotplate consumes only 11.8 mW when heated up to 400 °C. For reliability testing, the hotplate is continuously operated at higher temperatures. It was found that at 404 °C, 508 °C and 595 °C, the microhotplate continuously operated up to 16.5 h, 4.3 h and 4 min respectively without degrading its performance. It can sustain at least 53 cycles pulse-mode of operation at 540 °C with ultra-low resistance and temperature drifts. The structure has maximum current capability of 19.06 mA and it can also sustain the ultrasonic vibration at least for 30 min without any damage.     

Accurate operation of a CMOS integrated temperature sensor

A high-accuracy temperature sensor is designed by applying the temperature characteristics of substrate bipolar transistor in CMOS technology. Initial accuracy of the temperature sensor can be improved by chopper amplifiers and dynamic element matching. Using these two methods, the circuit realization of reference voltage is also described. Simulation results show that the inaccuracy is within×0.4 °C from ?40 to +100 °C. Experimental results, obtained from circuits fabricated in 0.5 μm CMOS process, indicate that the sensor is inaccurate within×0.7 °C from ?40 to +100 °C. The power dissipation is 0.35 mW and the chip area is 889 μm×620 μm. Compared with previously reported work, the temperature sensor in the paper has lower inaccuracy without calibration.     

Lifetime tests of 600-V GaN-on-Si power switches and HEMTs

We present the first systematic lifetime tests which show excellent long-term reliability for 600 V GaN-on-Si power switches.High voltage accelerated life testing in the OFF-state yields a field related mean-time-to-failure (MTTF) greater than 3 × 10⁸ h for a 600 V operating condition. High temperature accelerated testing in the ON-state gives an MTTF of about 6 × 10⁸h at a 150 °C use condition. High temperature operating life testing using hard switched boost converters at 175 °C shows no measurable device degradation after 3000 h of operation. These results show that the intrinsic reliability of the new device technology is more than adequate for commercial and industrial power electronics applications.     

Reliability of Cu nanoparticle joint for high temperature power electronics

Power cycle reliability of Cu nanoparticle joint has been studied for high temperature operation of power devices. Al₂O₃ heater chips and Cu–65 wt% Mo baseplates were joined by Cu nanoparticles and Sn–0.7Cu and power cycle tests of 65/200 °C and 65/250 °C were carried out on the joints. The Cu nanoparticles were prepared by reducing Cu carbonate in ethylene glycol with dodecanoic acid + dodecyl amine (C12) and decanoic acid and decyl amine (C10) as capping agents. A power cycle test of 65/200 °C did not inflict severe damage on the Cu nanoparticle joints so that there were not many cracks formed after 3000 cycles. Vertical cracks were formed in the C12 Cu nanoparticle joint after 3000 cycles of 65/250 °C test, however the maximum temperature during the power cycle test did not change at all because vertical cracks did not have an effect on preventing heat flow. On the contrary, lateral cracks were completely formed in the Sn–0.7Cu soldered joint after 200 cycles of 65/200 °C test and in the C10 Cu nanoparticle joint after 360 cycles of 65/250 °C test. In these experiments, the maximum temperatures were rapidly increased because heat conduction was prevented across the formed lateral cracks.     

Low-temperature low-pressure die attach with hybrid silver particle paste

New types of die attach pastes comprising micron-sized Ag particles hybridized with submicron-sized Ag particles were considered as lead-free die attach materials for SiC power semiconductors. Micron-sized Ag particles in alcohol solvent were prepared by mixing the die attach paste with submicron-sized Ag particles. The alcohol vaporizes completely during sintering and no residue exists in the bonding layer. The Ag layer has a uniform porous structure. The electrical resistivity of the printed tracks decreases below 1 × 10^?5 Ω cm when sintered above 200 °C. When sintered at 200 °C for 30 min, the average resistivity reaches 5 × 10^?6 Ω cm, which is slightly higher than the value obtained by using Ag nanoparticle paste. A SiC die was successfully bonded to a direct bonded copper substrate and the die-shear strength gradually increases with the increase in bonding temperature up to 300 °C. The Ag die attach bond layer was stable against thermal cycles between ?40 °C and 300 °C.     

Characteristics of ZnOV2O5MnO2Nb2O5Er2O3 semiconducting varistors with sintering processing

The effects of sintering temperature on the microstructure, electrical properties, and dielectric characteristics of ZnOV₂O₅MnO₂Nb₂O₅Er₂O₃ semiconducting varistors have been studied. With increase in sintering temperature the average grain size increased (4.5–9.5 μm) and the density decreased (5.56–5.45 g/cm³). The breakdown field decreased with an increase in the sintering temperature (6214–982 V/cm). The samples sintered at 900 °C exhibited remarkably high nonlinear coefficient (50). The donor concentration increased with an increase in the sintering temperature (0.60×10¹⁸–1.04×10¹⁸ cm^?3) and the barrier height exhibited the maximum value (1.15 eV) at 900 °C. As the sintering temperature increased, the apparent dielectric constant increased by more than four-fold.     

Reliability of high voltage/high power L/S-band Hbt technology

This paper presents the qualification methodology and results of an InGaP HBT process industrialised by UMS to cover high power L and S band applications. The high level of robustness of the technology has been demonstrated with RF test up to 9 dB compression without any degradation. MTTF of 12 FIT/mm² of semiconductor at a junction temperature of 175 °C have been demonstrated based on more than 560,000 component hours. Also, following the activation period, an asymptotic decrease of the Beta is pointed out both at WLR and long term reliability test and modelled by a Black law. Activation energy between 0.52 and 0.75 eV and a Black factor between 1 and 2 was found. An original and complete failure analysis methodology including NIR emission microscopy, FIB and TEM analysis, have been used to characterised infant mortality for which the root cause is attributed to the propagation through the base–emitter junction of dislocation in the epitaxy. Activation energy of 0.58 eV was determined for this mechanism.     

Effect of substrate temperature on indium tin oxide (ITO) thin films deposited by jet nebulizer spray pyrolysis and solar cell application

This study focused on the effect of substrate temperature (350 °C, 400 °C, and 450 °C) on morphological, optical, and electrical properties of indium tin oxide (ITO) films deposited onto porous silicon/sodalime glass substrates through jet nebulizer spray pyrolysis for use in heterojunction solar cells. X-ray diffraction analysis confirmed the formation of pure and single-phase In₂O₃ for all the deposited films whose crystallinity was enhanced with increasing substrate temperature, as shown by the increasing (222) peak intensity. Morphological observations were conducted using scanning electron microscopy to reveal the formation of continuous dense films composed of nanograins. The UV–vis spectra revealed that the transmittance increased with increasing substrate temperature, reaching a value of over 80% at 450 °C. The photoelectric performance of the solar cell was studied using the I–V curve by illuminating the cell at 100 mW/cm². A high efficiency (η) of 3.325% with I_sc and V_oc values of 14.8 mA/cm² and 0.60 V, respectively, was attained by the ITO solar cell annealed at 450 °C.     

Non-ohmic effect and pulse aging behavior of V/Mn/Co/Bi/Dy co-doped ZnO semiconducting varistors with sintering processing

We examined the effect of sintering on the microstructure, non-ohmic properties, clamping characteristics, and pulse aging behavior of V/Mn/Co/Bi/Dy codoped ZnO semiconducting varistors. The average grain size increased from 4.7 to 10.4 µm and the densities of the sintered pellets decreased from 5.47 to 5.37 g/cm³ with the increase in sintering temperature. The maximum non-ohmic coefficient (35.3) was obtained at a sintering temperature of 900 °C. Varistors sintered at 900 °C exhibited the best clamp characteristics, a clamp voltage ratio of 1.74–2.54 at a pulse current of 1–25 A. Varistors sintered at 925 °C exhibited the strongest electrical stability; variation rates for the breakdown field measured at 1.0 mA/cm², for the non-ohmic coefficient, and for the leakage current density were 3.4%, 6.6%, and −11.2%, respectively, after application of a pulse current of 100 A.