Optimized 2.4 GHz voltage controlled oscillator with a high-Q MWCNT network-based pulse-shaped inductor

This paper focuses on the use of a high-Q Multi-Wall Carbon Nano-Tube (MWCNT)-based pulse-shaped inductor in the implementation of an LC differential voltage-controlled oscillator (LCVCO). The topology integrates a micro-scaled capacitor and a MWCNT network-based inductor together with the CMOS circuits. The CMOS circuits were designed to enhance the quality factor and to control the oscillation amplitude. The high quality factor of the inductor improves the overall quality factor and phase noise of the oscillator. The measurement results show that the LCVCO operates at 2.3982 GHz and achieves a phase noise of ?133.3 dBc/Hz at 1 MHz away from the carrier frequency. The VCO produces frequency tuning from 2.07 GHz to 2.77 GHz (29.16%) with an ultra low power consumption of 1.7 mW from a 0.6 V supply voltage. The output power level of the VCO is ?10 dBm, with an improved quality factor of 49.     

Low-power CMOS LC QVCO using zero-biased transistor coupling of MWCNT network-based VCO structure

This paper presents design, analysis and implementation of a 2.4 GHz QVCO (Quadrature Voltage Controlled Oscillator), for low-power, low-voltage applications. Cross coupled LC VCO (Inductor–Capacitor Voltage Controlled Oscillator) topology realized using integration of a micro-scaled capacitor and a MWCNT (Multi-Wall Carbon Nano-Tube) network based inductor together with the CMOS circuits is utilized together with MOS transistors as coupling elements to realize QVCO. With the passive coupling achieved from the MOS transistors, power consumption is minimized while maintaining a small chip area. The variable capacitors and the inductors are designed using ANSYS and imported through DAC components in ADS (Advanced Design software). Accurate simulation of the QVCO is performed in the software environments and the results are provided. The measurement results show that the QVCO provides quadrature signals at 2.4 GHz and achieves a phase noise of −130 dBc/Hz 1 MHz away from the carrier frequency. The VCO produces frequency tuning from 2.1 GHz to 2.60 GHz (20.83%) with a control voltage varying from 0 to 0.3 V. It achieves a peak to peak voltage of 0.59 V with an ultra low power consumption of 3.8 mW from a 0.6 V supply voltage. The output power level of the QVCO is −10 dBm, with an improved quality factor of 45. The phase error of the QVCO is measured as 3.1°.     

Floating active inductor based Class-C VCO with 8 digitally tuned sub-bands

A fully integrated floating active inductor based voltage-controlled oscillator (VCO) is presented. The active inductor employs voltage differencing transconductance amplifier (VDTA) as a building block. The designed VCO achieves frequency tuning by varying the bias current through the VDTA and utilizes a Class-C topology for improving the phase noise performance. The inductor-less VCO is designed and implemented in a 45-nm CMOS process and its performance is estimated using Virtuoso ADE of Cadence. Operating at a supply voltage of ±1 V, the proposed VCO consumes 0.44–1.1 mW corresponding to the oscillation frequency of 1.1–1.8 GHz thereby exhibiting a tuning range of 48.27%. The phase noise of the VCO lies in the range of −94.12 to −98.37 dBc/Hz at 1 MHz offset resulting in a FOM of −172.14 to −176.69 dBc/Hz.     

A wide-range VCO with an automatic frequency,amplitude and gain calibration loop

This paper presents a wide tuning range VCO with an automatic frequency, amplitude and gain calibration loop. To cover the wide tuning range, the automatic frequency calibration (AFC) loop is used. In addition, to provide the optimum Negative-Gm to the LC tank in a wide frequency range, the number of active Negative-Gm circuits is designed to be switched digitally based on the target frequency. Also, the VCO gain should be calibrated digitally to compensate for the gain variation. The VCO tuning range is 2.6 GHz, from 1.7 to 4.3 GHz, and the power consumption is 2–4 mA from a 1.8 V supply. The measured VCO phase noise is −120 dBc/Hz at 1 MHz offset.     

Dual-resonance concurrent oscillator

This paper studies a new dual-band CMOS class-C voltage-controlled oscillator (VCO). The oscillator consists of a dual-resonance LC resonator in shunt with two pairs of capacitive cross-coupled nMOSFETs. The proposed oscillator has been implemented with the TSMC 0.18 μm CMOS technology, and it shows a frequency tuning range with two frequency bands and a small tuning hysteresis is measured. The oscillator can generate differential signals at 2.4 GHz and 6.9 GHz and it also can generate concurrent frequency oscillation while the circuit is biased around the bias with frequency tuning hysteresis. With the supply voltage of V_DD = 1.1 V, the VCO-core current and power consumption of the oscillator are 2.90 mA and 3.19 mW, respectively. The die area of the class-C oscillator is 0.9 × 0.97 mm². Overvoltage stress is applied to the oscillator, measurement indicates the concurrent oscillation is sensitive to overvoltage stress.     

Improving linearity in MOS varactor based VCOs by means of the output quiescent bias point

This paper presents a CMOS based LC tank VCO topology improving the tuning range linearity. The VCO tuning range is linearized with PMOS varactors which remain in the inversion region for an extended range of the control voltage. This is achieved with the design of the quiescent operating point in the VCO's output nodes with a value close to the voltage rails, letting the varactors to behave quasi linearly in the achievable VCO tuning range. The experimental results of a VCO in a CMOS 0.35 µm process show a linear tuning range improvement of 75% of the control voltage in the (1.43–1.55) GHz range, with a minimum VCO gain variation compared to similar architectures. The results show a phase noise improvement from −94 dBc/Hz to −124 dBc/Hz @600 kHz offset from the carrier with an overall reduced amplitude noise for the VCO.     

0.8 V PLL-based automatic frequency tuning system for current-mode filters

A wide-range automatic frequency tuning system for current-mode filters is proposed in this paper. The cutoff frequency of the tunable filter is controlled by an external reference signal and is locked in the desired frequency through a current-mode based phase locked loop (PLL) circuit. Although the PLL operates in a relatively narrow band, the total tuning range of the topology is extended by interpolating an automatic frequency detector after the reference input and before the PLL. The use of current controlled oscillator, based on same blocks with those in the filter, offers accuracy and feasible design in the control path. The topology has been simulated using MOS transistor models for a 130 nm CMOS technology in 0.8 V supply voltage. The achieved overall automatic tuning range was from 2.3 MHz to 660 MHz.     

A low phase noise and low power 3–5 GHz frequency synthesizer in 0.18 µm CMOS technology

A low power frequency synthesizer for WLAN applications is proposed in this paper. The NMOS transistor-feedback voltage controlled oscillator (VCO) is designed for the purpose of decreasing phase noise. TSPC frequency divider is designed for widening the frequency range with keeping low the power consumption. The phase frequency detector (PFD) with XOR delay cell is designed to have the low blind and dead zone, also for neutralizing the charge pump (CP) output currents; the high gain operational amplifier and miller capacitors are applied to the circuit. The frequency synthesizer is simulated in 0.18 µm CMOS technology while it works at 1.8 V supply voltage. The VCO has a phase noise of −136 dBc/Hz at 1 MHz offset. It has 10.2% tuning range. With existence of a frequency divider in the frequency synthesizer loop the output frequency of the VCO can be divided into the maximum ratio of 18. It is considered that the power consumption of the frequency synthesizer is 4 mW and the chip area is 10,400 µm².     

A 84% tuning range, 4.3-GHz VCO with two-step negative-G<Subscript>m</Subscript> tuning and amplitude calibration loop

This paper presents wideband, low voltage CMOS LC-VCO with automatic two-step amplitude calibration loop to compensate the PVT variation. To cover the wide tuning range, digital automatic negative-G_m tuning loop and analog automatic amplitude calibration loop are proposed. The power consumption is 2–6 mA from a 1.2 V supply. The VCO tuning range is 3.4 GHz, from 2.35 to 5.75 GHz. The measured phase noise is −117 dBc/Hz at the 1 MHz offset when the center frequency is 4.313 GHz.     

High-resolution wide-band LC-VCO for reliable operation in phase-locked loops

This paper presents a novel sizing scheme to implement the array of switches in the capacitor bank of LC-VCOs for oscillation frequency coarse control. The proposed scheme allows increasing the number of elements in the capacitor bank beyond the values typically achieved by binary scaling, endowing the resulting LC-VCO with a wider tuning range and high frequency resolution, which is beneficial for the implementation of reliable phase-locked loops. Two different gigahertz LC-VCOs have been designed to validate the proposed scheme. The prototypes, fabricated in a cost-effective 0.18 μm CMOS process, cover a 700 MHz frequency range from 1.35 GHz to 2.05 GHz and from 2.05 GHz to 2.75 GHz, respectively, with a phase noise figure of − 122 dBc/Hz and − 119.5 dBc/Hz at 1 MHz from the mid-range carriers, and a power consumption of 18 mW. These figures result in a respective FOM_T of − 186.4 dBc/Hz and − 183.8 dBc/Hz. The performance of the fabricated LC-VCOs is achieved in each case with a dense coarse tuning range of 128 levels, which allows, respectively, a fine tuning gain smaller than 40 MHz V^− 1.     

Wide-tuning-range,low-phase-noise quadrature ring oscillator exploiting a novel noise canceling technique

This paper presents a novel noise-canceling technique, which is used to improve the phase noise of a two-stage quadrature ring oscillator. The thermal noise canceling circuitry is used to cancel the channel thermal noise of the output transistors in each stage of the oscillator. Simulations using TSMC 0.13 μm CMOS technology show a wide frequency tuning range of 315 MHz to 6.64 GHz and ?97.5 dBc/Hz at 1 MHz offset from 4.7 GHz for changing supply from 0.5 V to 1.6 V. The power consumption is obtained to be 14.8 mW. The proposed oscillator can be used in applications such as ultra-wideband systems, and multiband and multimode receivers.     

A quadrature RC-oscillator with capacitive coupling

In this paper the capacitive coupling in quadrature RC-oscillators is investigated. The capacitive coupling has the advantages of being noiseless with a small area penalty and without increasing the power dissipation. The results show that a phase error below 1° and an amplitude mismatch lower than 1% are obtained with a coupling capacitance about 20% of the oscillator׳s capacitance value. Due to this kind of coupling, the phase-noise improves by 3 dB (to −115.1 dBc/Hz @ 10 MHz) and the increase of power requirement is only marginal leading to a figure-of-merit of −154.8 dBc/Hz. This is comparable to the best state-of-the-art RC-oscillators, yet the dissipated power is about four times less. We present calculations of frequency, phase error and amplitude mismatch that are validated by simulations. The theory shows that phase error is proportional to the amplitude mismatch, indicating that an automatic phase error minimization based on the amplitude mismatches is possible. The measurements on a 2.4 GHz voltage-controlled quadrature RC-oscillator with capacitive coupling fabricated in 130 nm CMOS circuit prototypes validate the theory.     

Common-base multi-finger submicron InGaAs/InP double heterojunction bipolar transistor with fmax of 305 GHz

A layout of a common-base four-finger InGaAs/InP double heterostructure bipolar transistor (DHBT) has been designed and the corresponding DHBT has been fabricated successfully by using planarization technology. The area of each emitter finger was 1 × 15 μm². The breakdown voltage was more than 7 V, the current could be more than 100 mA. The maximum output power can be more than 80 mW derived from the DC characteristics. The maximum oscillation frequency was as high as 305 GHz at I_C = 50 mA and V_CB = 1.5 V. The DHBT is thus promising for the medium power amplifier and voltage controlled oscillator (VCO) applications at W band and higher frequencies.     

A compact low-profile dual-band antenna for WLAN and WAVE applications

A compact and low-profile patch antenna with a simple structure is presented for the wireless local-area network (WLAN) and the wireless access in the vehicular environment (WAVE) applications. The proposed antenna with an overall size of only 23 mm × 25 mm is fed by a coplanar waveguide (CPW), and yields 10-dB impedance bandwidths of about 250 MHz centered at 2.44 GHz and of about 22% ranging from 5.13 to 6.38 GHz suitable for the WLAN 2.4/5.2/5.8 GHz and the WAVE 5.9 GHz (IEEE 802.11p) applications. Also, good dipole-like patterns and high average antenna gain of ≥2.3 dBi over the operating bands have been obtained. In this design, resonance can be effectively controlled by simply tuning the shaped slots on the patch. Mechanism of mode excitations and effect of the added slot's length on resonance for the proposed antenna are examined and discussed in detail. The experimental results have validated the proposed design as useful for modern mobile communication.     

A technique to improve the linearization of frequency–voltage characteristic of LC-VCO

This paper presents a very low-power linearization technique to improve the linearity of frequency-voltage characteristic of LC-VCO (voltage controlled oscillator) using MOS varactor. This reduces the VCO gain (K _VCO) variation and its required value over the tuning voltage range. Low K _VCO improves noise and reference spur performances at the output of phase lock loop/frequency synthesizer (FS). Low K _VCO variation reduces FS loop stability problem. Using this VCO circuit, a fully on-chip integer-N frequency synthesizer has been fabricated in 0.18 μm epi-digital CMOS technology for 2.45 GHz ZigBee application. The measured VCO phase noise is ?115.76 and ?125.23 dBc/Hz at 1 and 3 MHz offset frequencies, respectively from 2.445 GHz carrier and the reference spur of the frequency synthesizer is ?68.62 dBc. The used supply voltage is 1.5 V.     

An Inductor-less Sub-mW Low Noise Amplifier for Wireless Sensor Network Applications

This paper presents a Sub-mW differential Common-Gate Low Noise Amplifier (CGLNA) for ZigBee standard. The circuit takes the advantage of shunt feedback and Dual Capacitive Cross Coupling (DCCC) to reduce power consumption and the bandwidth extension capacitors to support 2.4 GHz ISM band. An amplifier employing these techniques has been designed and simulated in 0.18 µm TSMC CMOS technology. The Simulation results show a gain of 18.2 dB, an IIP3 of −4.32 dBm and a noise figure of 3.38 dB at 2.4 GHz. The proposed LNA consumes only 967 µW from a 1-V supply.     

Low power dissipation SiGe HBT dual-band variable gain amplifier

A dual-band variable gain amplifier operating at 0.9 GHz and 2.4 GHz was designed based on high performance RF SiGe HBT for large amount of signals transmission and analysis. Current steering was adopted in gain-control circuit to get variable trans-conductance and then variable gain. Emitter degeneration and current reuse were considered in amplifying stage for low noise figure and low power dissipation respectively. A single-path circuit resonating at two frequency points simultaneously was designed for input impedance matching. PCB layout parasitic effects, especially the via parasitic inductor, were analyzed theoretically and experimentally and accounted for using electro-magnetic (EM) simulation. The measurement results show that a dynamic gain control of 26 dB/16 dB in a control voltage range of 0.0–1.4 V has been achieved at 0.9/2.4 GHz respectively. Both S₁₁ and S₂₂ are below than –10 dB in all the control voltage range. Noise figures at both 0.9 GHz and 2.4 GHz are lower than 5 dB. Total power dissipation of the dual-band VGA is about 16.5 mW at 3 V supply.     

Design of ultra-low voltage integrated CMOS based LNA and mixer for ZigBee application

This work describes the design and implementation of an ultra-low voltage, ultra-low power fully differential low noise amplifier (LNA) integrated with a down-conversion mixer for 2.4 GHz ZigBee application. An inductive-degenerated cascoded LNA is adapted and integrated with a double-balanced mixer which is targeted for low-power application. The proposed design has been extracted and simulated in a 0.13 μm standard CMOS technology. With a power consumption of 905 μW at a voltage headroom of 0.5 V, the proposed LNA-mixer integration reaches out to an integrated noise figure (NF) of 7.2 dB, a gain of 22.3 dB, 1 dB compression point (P1 dB) of −22.3 dBm and input-referred third-order intercept point (IIP3) of −10.8 dBm.     

A low-voltage low-power CMOS transmitter front-end using current mode approach for 2.4 GHz wireless communications

This paper presents a low-voltage low-power transmitter front-end using current mode approach for 2.4 GHz wireless communication applications, which is fabricated in a chartered 0.18 μm CMOS technology. The direct up-conversion is implemented with a current mode mixer employing a novel input driver stage, which can significantly improve the linearity and consume a small amount of DC current. The driver amplifier utilizes a transimpedance amplifier as the first stage and employs an inter-stage capacitive cross-coupling technique, which enhances the power conversion gain as well as high linearity. The measured results show that at 2.4 GHz, the transmitter front-end provides 15.5 dB of power conversion gain, output P?1 dB of 3 dBm, and the output-referred third-order intercept point (OIP3) of 13.8 dBm, while drawing only 6 mA from the transmitter front-end under a supply voltage of 1.2 V. The chip area including the testing pads is only 0.9 mm×1.1 mm.     

Low Voltage CMOS LC VCO with Switched Self‐Biasing

This paper presents a switched self‐biasing and a tail current‐shaping technique to suppress the 1/f noise from a tail current source in differential cross‐coupled inductance‐capacitance (LC) voltage‐controlled oscillators (VCOs). The proposed LC VCO has an amplitude control characteristic due to the creation of negative feedback for the oscillation waveform amplitude. It is fabricated using a 0.13 µm CMOS process. The measured phase noise is ‐117 dBc/Hz at a 1 MHz offset from a 4.85 GHz carrier frequency, while it draws 6.5 mA from a 0.6 V supply voltage. For frequency tuning, process variation, and temperature change, the amplitude change rate of the oscillation waveform in the proposed VCO is 2.1 to 3.2 times smaller than that of an existing VCO with a fixed bias. The measured amplitude change rate of the oscillation waveform for frequency tuning from 4.55 GHz to 5.04 GHz is 131 pV/Hz.