基于云计算的武器装备体系能力试验测试研究

针对武器装备体系能力试验测试的发展趋势和面临的问题,研究建立了基于云计算的武器装备体系能力试验测试模型。论述了模型中各个层次的组成和作用,阐述了引入云计算技术对武器装备体系能力试验带来的影响,划分了体系能力试验的测试阶段,提出了通用测试流程,并通过具体案例进行了详细阐述,形成了基于云计算的武器装备体系能力试验测试设计。     

装备测试性验证技术综述

装备测试性验证是指为检验设计和制造所赋予装备的测试性是否满足规定的测试性要求而进行的试验与评价工作,是装备故障预测与健康管理设计的重要依据,也是装备采办管理和科学决策的基础.如何有效地开展测试性验证试验,是理论和工程实践中亟待解决的问题,具有重要的理论和工程应用价值.综述了装备测试性验证技术的国内外发展现状,阐述了测试性验证的技术体系,分析了测试性验证的关键技术,指出了目前亟待解决的关键问题和难点问题,最后,在对当前测试性实物验证和非实物验证技术方案进行综合分析的基础上,对测试性验证技术方案进一步的研究发展给出了建议.     

基于测试性约束的鱼雷总体集成与测试研究

本文从测试与测试性、测试性与鱼雷总体集成测试等方面,开展了鱼雷武器装备在测试性约束条件下的总体集成与测试研究,可为后续鱼雷武器装备型号的总体集成与测试过程提供指导与参考.     

测试性试验的FMECA方法研究

故障模式、影响及危害性分析(FMECA)是开展测试性分析的重要基础之一.通过对某机载设备测试性验证试验实例中的FMECA的分析过程进行研究,提出了适用于测试性试验的FMECA方法,保证了FMECA分析工作的适用性和准确性,对于今后测试性试验的FMECA工作的开展具有一定的借鉴和指导意义.     

基于层次模糊决策的雷达装备测试性综合评估

针对目前雷达装备定型、交付验收时缺乏系统有效的测试性评估方法的问题,提出了基于层次模糊决策的雷达装备测试性综合评估模型。首先,从现代雷达装备测试性设计的根本任务和实现目标出发,建立了较为全面的雷达装备测试性评估指标体系。在此基础上,将层次分析法与模糊数学的方法引入到测试性评估中,以某型雷达装备验收时测试性定量验证和定性检查情况为例,对雷达装备测试性进行了综合评估。结果表明,该评估模型简单、实用、有效,为复杂武器装备的测试性评估提供了新思路。     

机电设备的测试性验证方法初探

针对目前机电设备缺少有效的测试性验证方法的问题,提出了机电设备测试性验证方法与步骤.通过采取基于故障影响相对比值的样本分配方案,可以使试验结果更加真实、可信.根据注入故障必须不能破坏任何设备的原则,对于串联型机电设备中不宜直接进行故障注入的目标,可以通过后驱动技术进行故障注入.最后,对某串联型机电设备进行了测试性验证,...     

一种面向板级电路的故障注入系统设计

在装备测试性验证过程中,故障注入是一项关键技术。针对于装甲装备测试性设计不足的情况,利用已有实验条件,通过对电路中故障进行分类,设计实现了对应的模拟故障板,对某型坦克炮控系统中的电路板进行了故障注入,用故障检测设备检测到故障的存在,通过分析测试性验证数据,为装备BIT研究以及测试性设计的提高提供了依据。     

机载电子装备测试性验证平台设计与实现

针对现代机载电子装备在执行任务过程中故障检测和隔离难度大、维修保障困难等问题,利用故障注入的方法设计了机载电子装备测试性验证平台。首先,阐述了验证平台的总体架构、交联关系和工作原理;然后,基于PXI技术设计了测试性验证平台的自动测试分系统与故障注入分系统,并兼顾了适配接口模块;同时,验证平台集成VITE软件作为平台的故障注入软件开发环境;最后,对某机载配电系统测试信号及故障模式进行分析,开发了故障注入控制程序,为提高机载装备测试性水平提供了技术参考。     

在跌落撞击负载条件下的键合互连可靠性测试(英文)

在大多数移动通信装置的寿命中最常见的故障是通过跌落撞击产生的。这是当今通过跌落撞击测试的方法测得的,该方法已经通过了JEDEC标准。然而这种方法相当耗时,且复验性方面还存在着一些问题。报道的研究是在与焊凸冷拉相关联的跌落撞击测试情况下完成的,这两者之间可以替代。本研究方法旨在了解引起故障的机械负载,并不仅仅是适合于数据。因此,跌落撞击测试便成为一种模式并备用来验证这一模式的试验,它将成为未来的处理方式。完成的焊凸冷拉测试研究证实,该测试未将焊凸偏移至一种确定的故障模式,测试研究的结果以及有关焊凸的模拟情况一并作了阐述。两种测试似乎是测试了相同的现象,根据来自CBP(cold bump pull)的结果表明与跌落撞击测试的情况相同,但由于模拟和试验工作尚未完全结束,其中的详情暂无法提供。     

面向ATE的电路板测试性分析及评估方法研究

为了客观地评价TPS,保证ATE在电路板测试维修中发挥更大作用,给出了面向ATE的电路板测试性评估方法.通过ATE测试资源分析选择测试点,利用电路故障仿真,建立电路板的测试性模型、生成依赖矩阵,得出电路板故障检测率和隔离率;然后结合ATE测试的可靠性及费用分析,得到电路板平均故障隔离费用和平均故障隔离步数,实现了电路板测试性的综合评估.最后以某装备电路板为例,验证了方法的有效性.     

利用BIT技术提高雷达维修性

在现代复杂电子系统中,机内测试(BIT)技术作为提高系统可维修性和可测试性的重要手段,日益得到普遍重视和广泛应用。根据设计原则,BIT系统采用多机分布式结构,故障检测电路和故障检测软件采用通用化设计,故障定位采用基于故障传播有向图的故障定位方法。本文对雷达设备的维修性及状态监测方面进行了探索,主要阐述了机内测试系统的实现结构及其基于故障树算法实现故障定位的原理,介绍了通用故障检测电路的工作原理,总结了设计过程中应注意的问题及相应的解决方法。     

某型军用测试设备可测试性设计验证

在某型军用测试设备设计的初期就考虑可测试性要求,通过优化系统结构并以方便测试为目的进行系统设计,通过故障树的方法从系统层面对测试设备的可测试性进行分析并验证,可为其它测试设备的研制提供参考.     

面向综合诊断的电子装备测试资源优化分配

针对综合诊断思想对电子装备测试资源分配的新要求,在测试点优化的基础上,建立了装备BITE与ATE优化分配的模型。该模型以测试代价最小为优化目标,以故障检测率、故障隔离率及虚警率为约束条件并通过LINGO求解。结果表明,该方法在满足测试性指标的同时降低了测试代价,对装备分层次设计和诊断、提高保障效率、减少寿命周期费用,具有重要意义。     

A synthesis-based test generation and compaction algorithm for multifaults

Because of its inherent complexity, the problem of automatic test pattern generation for multiple stuck-at faults (multifaults) has been largely ignored. Recently, the observation that multifault testability is retained by algebraic factorization demonstrated that single fault (and therefore multifault) vector sets for two-level circuits could give complete multifault coverage for multilevel circuits constructed by algebraic factorization. Unfortunately, in using this method the vector set size can be much larger than what is really required to achieve multifault coverage, and the approach has some limitations in its applicability.In this article we first present a multifault test generation and compaction strategy for algebraically factored multilevel circuits, synthesized from two-level representations. We give a basic sufficiency condition for multifault testability of such networks.We next focus on the relationship between hazard-free robust path-delay-fault testability and multifault testability. We show that the former implies the latter for arbitrary multilevel circuits. This allows the use of previously developed composition rules that maintain path-delay-fault testability for the synthesis of multifault testable circuits.We identify a class of multiplexor-based networks and prove an interesting property of such networks—if the networks are fully single stuck-at fault testable, or made fully single stuck-at fault testable, they are completely multifault testable. We give a multifault test generation and compaction algorithm for such networks.We provide experimental results which indicate that a compacted multifault test set derived using the above strategies can be significantly smaller than the test set derived using previously proposed procedures. These results also indicate the substantially wider applicability of our procedures, as compared to previous techniques.     

半主动激光制导炸弹测试系统设计

针对某半主动激光制导炸弹的测试需求,设计了基于PXI总线的测试系统,同时研制了激光目标模拟器、数据链指令机等专用测试设备,利用RS422总线将相关专用测试设备与测试系统相连,并结合卫星信号模拟器构建了一套半主动激光制导武器测试系统。该系统可完成武器在挂飞段、攻击飞行段等整个工作过程的性能指标测试,保障了武器在整个研制、生产交付过程中的各种试验验证等工作。     

A New Testability Calculation Method to Guide RTL Test Generation

Current paper presents a unified approach for calculating mixed-level testability measures. In addition, a new method of testability guided RTL Automated Test Pattern Generation (ATPG) for sequential circuits is introduced. The methods and algorithms are based on path tracing procedures on decision diagrams. The previous known methods have been implemented in test synthesis and in guiding gate-level test generation. However, works on application of testability measures to guide high-level test generation are missing. The main aim of this paper is to bridge this gap. Current method is compared to a recent approach known from the test synthesis area. Experiments show that testability measures greatly influence the fault coverage in RT-level test generation with the proposed approach achieving the best results. Similar to earlier works, our research confirms that RT-level fault coverage is in correlation with logic level one.This revised version was published online in March 2005 with corrections to the cover date.     

A new DFT methodology for sequential circuits

This paper introduce a new design for testability methodology for sequential circuits based on input/output pin utilization which exploits the possibility of applying test patterns in parallel. The goal is to reduce the test application time maintaining the same fault coverage as the one obtained using full scan. The proposed procedure includes necessary and sufficient conditions which are easily incorporated in a design system and produce the required implementation. Successful experimental results are presented on benchmark circuits:IC test length is reduced on an average by 44% of full scan.This work is partly supported by research grants from the Natural Sciences and Engineering Research Council of Canada and equipment grants from the Canadian Microelectronics Corporation.