Voltage equaliser for Li–Fe battery

In this article, a voltage equaliser is proposed for a battery string with four Li–Fe batteries. The proposed voltage equaliser is developed from a flyback converter, which comprises a transformer, a power electronic switch and a resonant clamped circuit. The transformer contains a primary winding and four secondary windings with the same number of turns connected to each battery. The resonant clamped circuit is for recycling the energy of leakage inductance of the transformer and for performing zero-voltage switching (ZVS) of the power electronic switch. When the power electronic switch is switched on, the energy is stored in the transformer; and when the power electronic switch is switched off, the energy stored in the transformer will automatically charge the battery whose voltage is the lowest. In this way, the voltage of individual batteries in the battery string is balanced. The salient features of the proposed voltage equaliser are that only one switch is used, the energy stored in the leakage inductance of the transformer can be recycled and ZVS is obtained. A prototype is developed and tested to verify the performance of the proposed voltage equaliser. The experimental results show that the proposed voltage equaliser achieves the expected performance.     

Voltage–frequency converter for laser welding control

An experimental model of a voltage–frequency converter was realised and utilised for the control of the thermal behaviour by the laser welding of thermoplastic polymer materials. The input signal of 0–10?V comes from a thermal–optical real-time analysing device of the welding process. The output signal of 0–300?Hz is introduced to the input interface of a laser welding equipment, for setting the laser pulse frequency. Operation tests were performed on the laser welding equipment type HL 124P LCU. The pulses have rectangular waveform, with the amplitude of 20?V. The frequency is very stable, with deviations of less than 0.5?Hz. The waveform and the frequency response at the converter output are appropriate.     

Current–Voltage Characteristics of Two-Electrode Elements with Carbon Nanotubes

Planar two-electrode nonlinear elements using carbon nanotubes doped with platinum metals are created and investigated. Among the nanotubes, branched ones are found. If doped, these nanotubes take a regular form. With appropriate doping, limiting currents above 1 A are achieved. However, the problem of contact between carbon nanotubes and electrodes has yet to be solved.     

Analysis of the Temperature Dependence of the Capacitance–Voltage and Conductance–Voltage Characteristics of Au/TiO2(rutile)/n-Si Structures

The capacitance–voltage–temperature (C–V–T) and the conductance/angular frequency–voltage–temperature (G/ω–V–T) characteristics of Au/TiO₂(rutile)/n-Si Schottky barrier diodes (SBDs) were investigated over the temperature range from 200 K to 380 K by considering the series resistance effect. Titanium dioxide (TiO₂) was deposited on n-type silicon (Si) substrate using a direct-current (DC) magnetron sputtering system at 200°C. To improve the crystal quality, the deposited film was annealed at 900°C to promote a phase transition from the amorphous to rutile phase. The C ^?2 versus V plots gave a straight line in the reverse-bias region. The main electrical parameters, such as the doping concentration (N _D), Fermi energy level (E _F), depletion layer width (W _D), barrier height (ф _CV), and series resistance (R _S), of Au/TiO₂(rutile)/n-Si SBDs were calculated from the C–V–T and the G/ω–V–T characteristics. The obtained results show that ф _CV, R _S, and W _D values decrease, while E _F and N _D values increase, with increasing temperature.     

Analysis of Current–Voltage Characteristics in UV AlGaN Heterostructure FPAs

Journal of Communications Technology and Electronics - UV visible-blind and solar-blind 320 × 256 photodiode arrays based on AlxGa1 – xN heteroepitaxial structures (AlGaN HES) and...     

MOS Capacitance–Voltage Characteristics from Electron-Trapping at Dopant Donor Impurity

The capacitance versus DC-voltage formula from electron trapping at dopant impurity centers is derived for MOS capacitors by the charge-storage method. Fermi–Dirac distribution and impurity deionization are included in the DC-voltage scale. The low-frequency and high-frequency capacitances, and their differences and derivatives, are computed in the presence of an unlimited source of minority and majority carriers. The results show that their difference and their DC-voltage derivatives, are large and readily measurable, hence suitable as a method for characterizing the electronic trapping parameters at dopant impurity centers and for a number of lower power signal processing and device technology monitoring applications.     

Frequency Dependent Capacitance and Conductance–Voltage Characteristics of Nitride GaAs Schottky Diode

Semiconductors - A nitride GaAs Schottky diode have been fabricated by nitridation of GaAs substrates with thickness 0.7 nm of GaN layer. The capacitance–voltage C(V) and...     

Numerical Analysis of Current–Voltage Characteristics of LWIR nBn and p-on-n HgCdTe Photodetectors

We performed numerical analysis of the current–voltage characteristics of long-wavelength infrared unipolar HgCdTe nBn photodetectors and compared those results with those of conventional p-on-n HgCdTe photodiodes. A computer program was applied to explain in detail the impact of the charge carrier generation and recombination processes on current densities. In our model the carrier diffusion, thermal generation–recombination, band-to-band tunneling, trap-assisted tunneling (via states located at mercury vacancies as well as dislocation cores), and impact ionization are included as potential limiting mechanisms. To validate the model, we compared the theoretical predictions with experimental data of high-quality p-on-n photodiodes published in the literature.     

MOS Capacitance–Voltage Characteristics: IV. Trapping Capacitance from 3-Charge-State Impurities

Metal-Oxide-Semiconductor Capacitance-Voltage (MOSCV) characteristics containing giant carrier trapping capacitances from 3-charge-state or 2-energy-level impurities are presented for not-doped, n-doped, p-doped and compensated silicon containing the double-donor sulfur and iron, the double-acceptor zinc, and the amphoteric or one-donor and one-acceptor gold and silver impurities. These impurities provide giant trapping capacitances at trapping energies from 200 to 800 meV (50 to 200 THz and 6 to 1.5 μm), which suggest potential sub-millimeter, far-infrared and spin electronics applications.     

Impurity Deionization Effects on Surface Recombination DC Current–Voltage Characteristics in MOS Transistors

Impurity deionization on the direct-current current–voltage characteristics from electron–hole recombination (R-DCIV) at SiO₂/Si interface traps in MOS transistors is analyzed using the steady-state Shockley-Read-Hall recombination kinetics and the Fermi distributions for electrons and holes. Insignificant distortion is observed over 90% of the bell-shaped R-DCIV curves centered at their peaks when impurity deionization is excluded in the theory. This is due to negligible impurity deionization because of the much lower electron and hole concentrations at the interface than the impurity concentration in the 90% range.     

Study of the Current–Voltage Characteristics of InAsSb-Based LED Heterostructures in the 4.2–300 K Temperature Range

Semiconductors - The results of a study in the temperature range 4.2–300 K of the current–voltage characteristics of light emitting diode (LED) heterostructures with an active region...     

Analysis of Current–Voltage Measurements on Long-Wavelength HgCdTe Photodiodes Fabricated on Si Composite Substrates

We have performed a detailed study of dark current versus voltage to understand existing limitations in dark current and address the nonuniformity of dark current in devices fabricated on HgCdTe grown on silicon substrates. One interesting observation is that trap-assisted tunneling, g-r currents, are not found close to zero bias in certain devices. Devices from the low end of the R ₀ A distribution show heavy shunting paths close to zero bias. We believe that these shunting paths may be the limiting cause of tail distributions in fabricated focal plane array tail distributions. Possible causes for these shunting paths are surface charges associated with dislocation cores and impurity gettering at dislocation cores. The measured non-anti-reflection (AR)-coated quantum efficiency (QE) was 0.576 at 78 K and displays the classical response versus wavelength. The measured QE on isolated single devices is consistent with the 256 × 256 focal-plane array mean QE. Obtained average dark currents are on the order of mid 10⁻⁵ A cm^–2, which is one order of magnitude higher than dark currents obtained from arrays on lattice-matched substrates. On average, arrays on lattice-mismatched substrates show performance characteristics inferior to those of arrays fabricated on lattice-matched substrates. This inferior performance is due to array pixel operability, as can be seen from the tail of the distribution and the average dark currents, which are one order of magnitude higher than those obtained on lattice-matched substrates.     

Model Development for Current–Voltage and Transconductance Characteristics of Normally-off AlN/GaN MOSHEMT

In this paper, an AlN/GaN-based MOSHEMT is proposed, in accordance to this, a charge control model has been developed analytically and simulated with MATLAB to predict the characteristics of threshold voltage, drain currents and transconductance. The physics based models for 2DEG density, threshold voltage and quantum capacitance in the channel has been put forward. By using these developed models, the drain current for both linear and saturation models is derived. The predicted threshold voltage with the variation of barrier thickness has been plotted. A positive threshold voltage can be obtained by decreasing the barrier thickness which builds up the foundation for enhancement mode MOSHEMT devices. The predicted I_d–V_gs, I_d–V_ds and transconductance characteristics show an excellent agreement with the experimental results and hence validate the model.     

Voltage Assisted Control of Spin-Transfer Nano-Oscillators

The spin-transfer nano-oscillator(STNO) has recently acquired a huge amount of research interest, due to its promising easy tunability along with the miniature size. The output frequency control of an STNO through magnetic field and current has been examined almost to its full extent; however, there are issues that still need to be addressed. Here, we propose a novel way of voltage control of the output frequency of an STNO, and alongside reducing its power requirement.     

Resolver-DC Voltage转换电路的设计

详细叙述了Resolver—DC Voltage转换电路的工作原理和设计方法．并对研制过程中所遇到的技术难点和关键技术进行了重点阐述。     

Compact Threshold Voltage Model for FinFETs

A 2D analytical electrostatics analysis for the cross-section of a FinFET (or tri-gate MOSFET) is performed to calculate the threshold voltage.The analysis results in a modified gate capacitance with a coefficient Ｈ introduced to model the effect of trigates and its asymptotic behavior in 2D is that for double-gate MOSFET.The potential profile obtained analytically at the cross-section agrees well with numerical simulations.A compact threshold voltage model for FinFET,comprising quantum mechanical effects,is then proposed.It is concluded that both gate capacitance and threshold voltage will increase with a decreased height,or a decreased gate-oxide thickness of the top gate，which is a trend in FinFET design.     

New Curvature-Compensated CMOS Bandgap Voltage Reference

A novel curvature-compensated CMOS bandgap voltage reference is presented. The reference utilizes two first order temperature compensations generated from the nonlinearity of the finite current gain β of vertical pnp bipolar transistor. The proposed circuit, designed in a standard 0.18 μm CMOS process, achieves a good temperature coefficient of 2.44 ppm/℃ with temperature range from --40℃ to 85 ℃, and about 4 mV supply voltage variation in the range from 1.4 V to 2.4 V. With a 1.8 V supply voltage, the power supply rejection ratio is -56dB at 10MHz.     

Effects of H2O Pretreatment on the Capacitance–Voltage Characteristics of Atomic-Layer-Deposited Al2O3 on Ga-Face GaN Metal–Oxide–Semiconductor Capacitors

Atomic layer deposition (ALD) of Al₂O₃ on Ga-face GaN is studied with respect to the effects of growth saturation, precursor injection sequence, and H₂O pretreatment. A metal–oxide–semiconductor capacitor (MOSCAP) structure is fabricated to measure the capacitance–voltage (C–V) characteristics. The origin of C–V hysteresis is explained by a model considering the different trapping behaviors of interface states and oxide border traps. The interface state density (D _it) is extracted as a function of band bending using an ultraviolet (UV)-assisted method. It is found that H₂O pretreatment followed by saturated ALD growth produces the best interface quality, with a reduced D _it compared with growth without H₂O pretreatment.     

Technique for the Electrochemical Capacitance–Voltage Profiling of Heavily Doped Structures with a Sharp Doping Profile

Semiconductors - The specific features of applying electrochemical capacitance–voltage profiling to investigate heavily doped structures with a sharp doping profile are considered. Criteria...     

The Effect of Ballistic Conduction Electrons on the Current–Voltage Characteristics of Thin-Film Bismuth-Based Cross-Shaped Microstructures

A decrease in the residual pressure to 10^–6 Pa during the deposition of bismuth films results in low-temperature metallic conductance of the films. Cross-shaped microstructures made of these films exhibit the property of ballistic transport, which is typical of two-dimensional systems. This property shows up as a bend of the current–voltage characteristics (CVCs). The value of bend resistance changes in inverse proportion to the width of interconnects and drops with increasing temperature in the range of 4.2–77 K. The free path of conduction electrons, are responsible for the CVC bend, was estimated at more than 1 m.