Fully depleted silicon on insulator MOSFETs on (1 1 0) surface for hybrid orientation technologies

Effective memory performance of the nonvolatile memory/thin film transistor (NVM/TFT) devices needs good TFT characteristics. The reduction in leakage current of the TFT devices was accomplished with the gate offset (GOF) structure. A simplified fabrication process for the GOF NVM is introduced in this study using the insulator over-etching approach. Nonvolatile memory devices on glass using SiO₂/SiO_x/SiO_xN_y stack with an offset length of 0, 0.2, 0.4, and 0.6 μm were investigated. The highly selective etching process and the short offset length help to avoid the problem of the gate aluminum collapsing on the source/drain electrodes. The TFT characteristics of the GOF structures displayed the remarkable improvement in leakage from 1.1 × 10⁻¹¹ A, for the TFT without an offset region, to the low OFF current of 1.34 × 10⁻¹² A for the device with a 0.6 μm offset length. The longer offset length gave the lowest OFF current. The degradation in transconductance and the threshold voltage was negligible with the g_m values of about 3 × 10⁻⁶ S and ΔV_th of about 0.2 V, respectively. The switching characteristics remained similar for all the devices. Additionally, the GOF structures slightly enhanced the retention characteristics. The memory window of the NVM without the offset after a retention time of 10,000 s was 58%, lower than the over 69% of the GOF devices. Therefore, the application of the GOF structure to reduce the leakage of the NVM/TFT proved to be effective.     

A study on the heat dissipation of high power multi-chip COB LEDs

In this study, the heat dissipation efficiencies of high power multi-chip COB (Chip-on-Board) LEDs with five different chip gaps were compared by assessing their junction temperature (T_j) and thermal resistance (R_th). Junction temperatures were measured using an IR camera and were also simulated by computational fluid dynamics (CFD) software. The effects of heat sinks with different surface areas, heat slugs made of different materials and different injection currents (different wattages) on high power LED junction temperatures are discussed. In addition, the optical characteristics of the LED, such as its lumens and luminous efficiency are evaluated. The experimental results show that a chip with a smaller gap has a higher junction temperature and more thermal resistance, and the junction temperature difference between the LEDs with the smallest and largest chip gaps is 3.12 °C. Optical performance analyses show that the LED with a larger chip gap has higher lumens and higher luminous efficiency. Thus, higher junction temperatures reduce the optical performance of high power LEDs.     

A 0.18 μm CMOS linear-in-dB AGC post-amplifier for optical communications

This paper presents a fully integrated 10GBase-LX4 Ethernet receiver front-end automatic gain control amplifier realized in a 0.18 μm CMOS process. Based on a very compact and reliable inductorless design, the proposed differential post-amplifier, comprises three main digitally programmable gain stages, a DC offset cancellation network and an automatic gain feedback control loop. Experimental results demonstrate a −3 dB cut-off frequency above 2.3 GHz over a −3 to 33 dB linear-in-dB controlled gain range with a sensitivity of 2.0 mV_p-p with a BER of 10⁻¹² at 2.5 Gb/s. For the aforementioned standard, 3.125 Gb/s, an input dynamic range above 50 dB is achieved, from 2.5 mV_p-p to 800 mV_p-p, indicating a BER of 10⁻¹². The chip core area is 0.3 × 0.3 mm² and it consumes 58 mW with a single supply voltage of 1.8 V.     

Unusual temperature dependence of electroluminescence intensity in blue InGaN single quantum well diodes

Temperature dependence of electroluminescence (EL) spectral intensity of the super-bright blue InGaN single quantum well (SQW) light emitting diodes (LEDs) has been carefully investigated over a wide temperature range (T=15-300 K) and as a function of injection current level (0.1-10 mA) in comparison with high quality GaAs SQW-LEDs. When T is slightly decreased to 180 K, the EL intensity efficiently increases in both cases due to the reduced non-radiative recombination processes. However, further decreasing T below 100 K, striking differences exist in EL intensity as well as injection current dependences between the two types of diodes. That is, the EL efficiency at lower T is found to be quite low for the blue diode in strong contrast to that of red GaAs SQW-LED where significant enhancement of the EL efficiency persists down to 15 K. These results indicate that the carrier capture efficiency of the blue SQW diode is unusually worse at lower T than at T=180-300 K, reflecting the unique radiative recombination processes under the presence of high-density dislocation (10¹⁰ cm⁻²).     

Au and non-Au based rare earth metal-silicide ohmic contacts to p-InGaAs

The aim of this study is to improve the electrical properties of ohmic contacts that plays crucial role on the performance of optoelectronic devices such as laser diodes (LDs), light emitting diodes (LEDs) and photodetectors (PDs). The conventional (Pd/Ir/Au, Ti/Pt/Au and Pt/Ti/Pt/Au), Au and non-Au based rare earth metal-silicide ohmic contacts (Gd/Si/Ti/Au, Gd/Si/Pt/Au and Gd/Si/Pt) to p-InGaAs were investigated and compared each other. To calculate the specific contact resistivities the Transmission Line Model (TLM) was used. Minimum specific contact resistivity of the conventional contacts was found as 0.111 × 10⁻⁶ Ω cm² for Pt/Ti/Pt/Au contact at 400 °C annealing temperature. For the rare earth metal-silicide ohmic contacts, the non-Au based Gd/Si/Pt has the minimum value of 4.410 × 10⁻⁶ Ω cm² at 300 °C annealing temperature. As a result, non-Au based Gd/Si/Pt contact shows the best ohmic contact behavior at a relatively low annealing temperature among the rare earth metal-silicide ohmic contacts. Although the Au based conventional ohmic contacts are thermally stable and have lower noise in electronic circuits, by using the non-Au based rare earth metal-silicide ohmic contacts may overcome the problems of Au-based ohmic contacts such as higher cost, poorer reliability, weaker thermal stability, and the device degradation due to relatively higher alloying temperatures. To the best of our knowledge, the Au and non-Au based rare earth metal-silicide (GdSi_x) ohmic contacts to p-InGaAs have been proposed for the first time.     

SiGe/Si quantum structures as a thermistor material for low cost IR microbolometer focal plane arrays

Uncooled microbolometer thermal infrared detector technology is presently revolutionizing the infrared technology field. Essential improvement of the cost/performance ratio would be achieved by microbolometer arrays with higher sensitivity, since this allows the use of simpler and less costly camera optics, which implies a lower cost of the complete IR camera. The sensitivity of the microbolometers depends critically on the signal-to-noise ratio of the integrated thermistor material, which is set by its temperature coefficient of resistance (TCR) and noise characteristics.In this work we have investigated the use of epitaxial silicon-germanium/silicon (SiGe/Si) quantum well (QW) structures as a thermistor material. Si_0.68Ge_0.32/Si QW structures typically give a TCR of 3.0%/K and low noise values. A calculation of the noise equivalent temperature NETD of a bolometer gives 25 mK using the following assumptions: f-number = 1, 30 Hz video frame rate for a 640 × 480 array, with a pixel size 25 × 25 μm.Higher TCR values are foreseen for SiGe/Si quantum dot structures, and the noise is expected to be similar to the QW based structures.     

Low threading dislocation density Ge deposited on Si (1 0 0) using RPCVD

Epitaxial Ge layer growth of low threading dislocation density (TDD) and low surface roughness on Si (1 0 0) surface is investigated using a single wafer reduced pressure chemical vapor deposition (RPCVD) system. Thin seed Ge layer is deposited at 300 °C at first to form two-dimensional Ge surface followed by thick Ge growth at 550 °C. Root mean square of roughness (RMS) of ∼0.45 nm is achieved. As-deposited Ge layers show high TDD of e.g. ∼4 × 10⁸ cm⁻² for a 4.7 μm thick Ge layer thickness. The TDD is decreasing with increasing Ge thickness. By applying a postannealing process at 800 °C, the TDD is decreased by one order of magnitude. By introducing several cycle of annealing during the Ge growth interrupting the Ge deposition, TDD as low as ∼7 × 10⁵ cm⁻² is achieved for 4.7 μm Ge thick layer. Surface roughness of the Ge sample with the cyclic annealing process is in the same level as without annealing process (RMS of ∼0.44 nm). The Ge layers are tensile strained as a result of a higher thermal expansion coefficient of Ge compared to Si in the cooling process down to room temperature. Enhanced Si diffusion was observed for annealed Ge samples. Direct band-to-band luminescence of the Ge layer grown on Si is demonstrated.     

RF power performance evaluation of surface channel diamond MESFETs

We experimentally investigate the large-signal radio frequency performances of surface-channel p-type diamond MESFETs fabricated on hydrogenated polycrystalline diamond. The devices under examination have a coplanar layout with two gate fingers, total gate periphery of 100 μm; in DC they exhibit a hole accumulation behavior with threshold voltage V_t ≈ 0-0.5 V and maximum drain current density of 120 mA/mm. The best small-signal radio frequency performances (maximum cutoff or transition frequency f_T and oscillation frequency f_max) were obtained close to the threshold and were of the order of 6 and 15 GHz, respectively. The power radio frequency response was characterized by driving the devices in class A at an operating frequency of 2 GHz and identifying through the active load-pull technique the optimum load for maximum power added efficiency. A power gain in linearity of 8 dB and an output power of approximately 0.2 W/mm with 22% power added efficiency were obtained on the optimum load impedance at a bias point V_DS = −14 V, V_GS = −1 V. To the best of our knowledge, these are the first large signal measurements ever reported for surface MESFET on polycrystalline diamond, and show the potential of such technology for the development of microwave power devices.     

Over 1000 V/30 mA operation GaN-on-Si MOSFETs fabricated on Si substrates

We demonstrated the operation of GaN-on-Si metal-oxide-semiconductor field effect transistors (MOSFETs) for power electronics components. The interface states at SiO₂/GaN were successfully improved by annealing at 800 °C for 30 min in N₂ ambient. The interface state density was less than 1 × 10¹¹ cm^-2 eV⁻¹ at E_c − 0.4 eV. The n⁺ contact layers as the source and drain regions as well as the reduced surface field (RESURF) zone were formed using a Si ion implantation technique with the activation annealing at 1200 °C for 10 s in rapid thermal annealing (RTA). As a result, we achieved an over 1000 V and 30 mA operation on GaN-on-Si MOSFETs. The threshold voltage was +2.6 V. It was found that the breakdown voltage depended upon the RESURF length and nitride based epi-layer thickness. In addition, we discussed the comparison of each performance of GaN-on-Si with -sapphire devices.     

Characteristic temperature of a tunneling-injection quantum dot laser: Effect of out-tunneling from quantum dots

A laser structure is studied, which exploits tunneling-injection of electrons and holes into quantum dots (QDs) from two separate quantum wells (QWs). An extended theoretical model is developed allowing for out-tunneling leakage of carriers from QDs into the opposite-to-injection-side QWs (electrons into the p-side QW and holes into the n-side QW). Due to out-tunneling leakage, parasitic recombination of electron-hole pairs occurs outside QDs – in the QWs and optical confinement layer. The threshold current density j_th and the characteristic temperature T₀ are shown to be mainly controlled by the recombination in the QWs. Even in the presence of out-tunneling from QDs and recombination outside QDs, a tunneling-injection laser shows potential for significant improvement of temperature stability of j_th – the characteristic temperature T₀ remains very high (above 300 K at room temperature) and not significantly affected by the QD size fluctuations.     

Material properties of anisotropic conductive films (ACFs) and their flip chip assembly reliability in NAND flash memory applications

In this paper, the material properties of anisotropic conductive films (ACFs) and ACF flip chip assembly reliability for a NAND flash memory application were investigated. Measurements were taken on the curing behaviors, the coefficient of thermal expansion (CTE), the modulus, the glass transition temperature (T_g), and the die adhesion strength of six types of ACF. Furthermore, the bonding processes of the ACFs were optimized. After the ACF flip chip assemblies were fabricated with optimized bonding processes, reliability tests were then carried out. In the pressure cooker test, the ACF with the highest adhesion strength showed the best reliability and the ACF flip chip assembly revealed no delamination at the chip-ACF interface, even after 96 h. In the high temperature storage test and the thermal cycling test, the reliability of the ACF flip chip assembly strongly depends on the T_g value of the ACF. In the thermal cycling test, in particular, which gives ACF flip chip assemblies repetitive shear stress, high value of CTE above T_g accelerates the failure rate of the ACF flip chip assembly. From the reliability test results, ACFs with a high T_g and a low CTE are preferable for enhancing the thermal and thermo-mechanical reliability. In addition, a new double-sided chip package with a thickness of 570 μm was demonstrated for NAND flash memory application. In conclusion, this study verifies the ACF feasibility, and recommends the optimum ACF material properties, for NAND flash memory application.     

Influence of thermal contact resistance on thermal impedance of microelectronic structures

The thermal impedance Z_th(jω) has been calculated numerically for a silicon chip glued on a ceramic substrate. The non perfect thermal contact is taken into account by modelling the chip-substrate interface as a thermal contact resistance r_c. If Z_th is represented as a Nyquist plot, mainly two circular arcs are observed. The high frequency arc is found to be almost independent from r_c, whereas the low frequency part is largely influenced by r_c. The thermal resistance R_th = Z_th(jω = 0) increases linearly with r_c, as known from the literature. Additionally, our simulations have shown that similar conclusions can be drawn for the real and imaginary part of Z_th at a fixed frequency ω ≠ 0.     

Low power resistive switching memory using Cu metallic filament in Ge0.2Se0.8 solid-electrolyte

Bipolar resistive switching memory device using Cu metallic filament in Au/Cu/Ge_0.2Se_0.8/W memory device structure has been investigated. This resistive memory device has the suitable threshold voltage of V_th > 0.18 V, good resistance ratio (R_High/R_Low) of 2.6 × 10³, good endurance of >10⁴ cycles with a programming current of 0.3 mA/0.8 mA, and 5 h of retention time at low compliance current of 10 nA. The low resistance state (R_Low) of the memory device decreases with increasing the compliance current from 1 nA to 500 μA for different device sizes from 0.2 μm to 4 μm. The memory device can work at very low compliance current of 1 nA, which can be applicable for extremely low power-consuming memory devices.     

Structural advantages of rectangular-like channel cross-section on electrical characteristics of silicon nanowire field-effect transistors

We have experimentally demonstrated structural advantages due to rounded corners of rectangular-like cross-section of silicon nanowire (SiNW) field-effect transistors (FETs) on on-current (I_ON), inversion charge density normalized by a peripheral length of channel cross-section (Q_inv) and effective carrier mobility (μ_eff). The I_ON was evaluated at the overdrive voltage (V_OV) of 1.0 V, which is the difference between gate voltage (V_g) and the threshold voltage (V_th), and at the drain voltage of 1.0 V. The SiNW nFETs have revealed high I_ON of 1600 μA/μm of the channel width (w_NW) of 19 nm and height (h_NW) of 12 nm with the gate length (L_g) of 65 nm. We have separated the amount of on-current per wire at V_OV = 1.0 V to a corner component and a flat surface component, and the contribution of the corners was nearly 60% of the total I_ON of the SiNW nFET with L_g of 65 nm. Higher Q_inv at V_OV = 1.0 V evaluated by advanced split-CV method was obtained with narrower SiNW FET, and it has been revealed the amount of inversion charge near corners occupied 50% of all the amount of inversion charge of the SiNW FET (w_NW = 19 nm and h_NW = 12 nm). We also obtained high μ_eff of the SiNW FETs compared with that of SOI planar nFETs. The μ_eff at the corners of SiNW FET has been calculated with the separated amount of inversion charge and drain conductance. Higher μ_eff around corners is obtained than the original μ_eff of the SiNW nFETs. The higher μ_eff and the large fractions of I_ON and Q_inv around the corners indicate that the rounded corners of rectangular-like cross-sections play important roles on the enhancement of the electrical performance of the SiNW nFETs.     

Influence of substrate thickness on thermal impedance of microelectronic structures

The thermal impedance Z_th(jω) has been calculated numerically, using the boundary element method, for a silicon substrate with a uniform heat source on top. The key feature is that the dynamic thermal behaviour is calculated directly in the frequency domain. The calculations were performed for a wide range of values for the thickness of the substrate. By representing the thermal impedance in a Nyquist plot (i.e. Im[Z_th(jω)] vs. Re[Z_th(jω)] with ω as parameter), mainly two circular arcs are observed. For the lower frequency arc, the impedance values as well as the frequency scale are found to be largely influenced by the substrate thickness. The arc corresponding to high frequencies on the other hand remains unchanged under thickness variations.Further analysis revealed an almost perfectly linear relationship between the thermal resistance R_th = Z_th(jω = 0) and the substrate thickness, even when the heat source is not centred on the substrate. Both the slope and intersection value obtained from the curve fitting can be explained by a simple geometrical model including the fixed-angle heat spreading approximation, used since many years in the literature.     

Thermal analysis of oxide-confined VCSEL arrays

A thermo-electric 3-D analysis of 980 nm vertical cavity surface emitting laser (VCSEL) arrays based on the finite element method (FEM) is presented in this paper. High performance VCSEL array structures with square mesas are modeled by applying a steady-state 3-D heat dissipation model. Several oxide aperture diameters (D_a), substrate thicknesses, current densities, array sizes, heat flux, and temperature profiles are considered. The analysis shows that the maximum internal temperature of a VCSEL array ranges from 306.5 K for a 20 μm D_a, 100 μm substrate thickness, 666 A/cm² current density, and a 1×1 array size to 412 K for a 5 μm D_a, 300 μm substrate thickness, 1200 A/cm² current density, and a 4×4 array size.     

Growth-direction-dependent characteristics of Ge-on-insulator by Si–Ge mixing triggered melting growth

The lateral liquid-phase epitaxy of Ge-on-insulator (GOI) using Si seeds has been investigated as a function of the Si-seed orientation and the growth direction. Giant single-crystalline GOI structures with ∼200 μm length are obtained using Si(1 0 0), (1 1 0), and (1 1 1) seeds. The very long growth is explained on the basis of the solidification temperature gradient due to Si-Ge mixing around the seeding area and the thermal gradient due to the latent heat around the solid/liquid interface at the growth front. In addition, growth with rotating crystal orientations is observed for samples with several growth directions. The rotating growth is explained on the basis of the bonding strength between lattice planes at the growth front. This rotating growth does not occur in any direction for (1 0 0) orientated seeds. Based on this finding the mesh-patterned GOI growth with a large area (250 μm × 500 μm) is demonstrated.     

Transient electroluminescence determination of carrier mobility and charge trapping effects in heavily doped phosphorescent organic light-emitting diodes

Transient electroluminescence (EL) was used to measure the delay between the excitation pulse and onset of emission in OLEDs based on phosphorescent bis[3,5-bis(2-pyridyl)-1,2,4-triazolato] platinum(ΙΙ) doped into 4,4′-bis(carbazol-9-yl) triphenylamine (CBP), from which an electron mobility of 3.2 × 10⁻⁶ cm²/V s was approximated. Delayed recombination was observed after the drive pulse had been removed and based on its dependence on frequency and duty cycle, ascribed to trapping and de-trapping processes associated with disorder-induced carrier localization at the interface between the emissive layer and electron blocker. The data suggests that the exciton recombination zone is at, or close to the interface between the emissive layer and electron blocker. Despite the charge trapping effects, a peak power efficiency of 24 lm/W and peak external quantum efficiency of 10.64% were obtained. Mechanisms for the electroluminescence and delayed recombination are proposed.     

Thermoelectric Power Generation Characteristics of a Thin-Film Device Consisting of Electrodeposited n-Bi2Te3 and p-Sb2Te3 Thin-Film Legs

A thermoelectric thin-film device of the cross-plane configuration was fabricated by flip-chip bonding of the top electrodes to 242 pairs of electrodeposited n-type Bi₂Te₃ and p-type Sb₂Te₃ thin-film legs on the bottom substrate. The electrodeposited Bi₂Te₃ and Sb₂Te₃ films of 20-μm thickness exhibited Seebeck coefficients of ?59 μV/K and 485 μV/K, respectively. The internal resistance of the thin-film device was measured as 3.7 kΩ, most of which was attributed to the interfacial resistance of the flip-chip joints. The actual temperature difference ΔT _G working across the thin-film legs was estimated to be 10.4 times smaller than the apparent temperature difference ΔT applied across the thin-film device. The thin-film device exhibited an open-circuit voltage of 0.294 V and a maximum output power of 5.9 μW at an apparent temperature difference ΔT of 22.3 K applied across the thin-film device.     

Mid-infrared (λ=2.775 µm) injection laser based on AlGaAsSb/InAs/CdMgSe hybrid double heterostructure grown by molecular-beam epitaxy

The lasing of an injection-pumped p-AlGaAsSb/n ⁰-InAs/n-CdMgSe double hybrid heterostructure in the mid-IR range is demonstrated for the first time. The lasing wavelength λ is 2.775 µm, and the threshold current density J _th=3–4 kA/cm² at T=77 K. The structure grown by two-stage molecular-beam epitaxy is characterized by extremely high (～1.5 eV) asymmetric potential barriers for electrons and holes in the InAs active region. The output power of spontaneous emission for round-mesa diodes at T=300 K was no less than 0.3 mW.