The anomalous avalanche breakdown

Normally, the breakdown voltage of a p-n junction decreases with increasing doping density. But there are also cases in which the breakdown voltage increases with increasing doping density, e.g., for InSb in the doping range from 10¹³cm^-3to 2 × 10¹⁴cm^-3. The reason for the anomalous behavior is the saturation of the ionization coefficient with increasing electric field strength. The anomalous behavior can only be observed if the tunnel breakdown requires a higher field strength as the one required for saturation of the ionization coefficient. This paper presents a rather simple theory yielding analytical solutions for the normal and anomalous avalanche breakdown. Treated is the influence of the doping profile upon the breakdown voltage in plane junctions and the influence of the radius of curvature for cylindrical one-sided abrupt junctions. The influence of the temperature upon the breakdown voltage and the multiplication factor as function of voltage is calculated for one-sided abrupt plane junctions. Finally, the temperature and doping range for the anomalous avalanche breakdown and the transition region is plotted for the semiconductors InSb, InAs, CdHgTe, PbSnTe, Ge, Si, GaAs, and GaP.     

Effect of impact ionization in the InGaAs absorber on excess noise of avalanche photodiodes

The effects of impact ionization in the InGaAs absorption layer on the multiplication, excess noise and breakdown voltage are modeled for avalanche photodiodes (APDs), both with InP and with InAlAs multiplication regions. The calculations allow for dead space effects and for the low field electron ionization observed in InGaAs. The results confirm that impact ionization in the InGaAs absorption layer increases the excess noise in InP APDs and that the effect imposes tight constraints on the doping of the charge control layer if avalanche noise is to be minimized. However, the excess noise of InAlAs APDs is predicted to be reduced by impact ionization in the InGaAs layer. Furthermore the breakdown voltage of InAlAs APDs is less sensitive to ionization in the InGaAs layer and these results increase tolerance to doping variations in the field control layer.     

Ideal FET doping profile

Using variational calculus it is possible to show, for each MOSFET voltage and device topology, that there exists an ideal drain region doping profile which yields the optimum resistance versus breakdown voltage tradeoff. Because of the inclusion, in the resistance, of the effects of spreading resistance this profile tends to have a higher doping concentration (lower resistivity) at the blocking junction, this point being at or near the point of maximum spreading resistance, a minimum in doping partway into the drain and then asymptotically approach a(1 - X/W)^{-1/2}form as derived by Hu [1] at the edge of the depletion layer. The theory and calculations in this paper compare the Hu profile, a constant profile and our optimum profile for various practical geometries over a range of breakdown voltages. It is shown that the higher the device voltage and the less important the spreading resistance effects, the closer the ideal profile approaches that of Hu. The ideal profile concept applies equally well to other FET or majority carrier (resistive) devices.     

Unified Breakdown Model of SOI RESURF Device with Uniform/Step/Linear Doping Profile

A unified breakdown model of SOI RESURF device with uniform,step，or linear drift region doping profile is firstly proposed.By the model,the electric field distribution and breakdown voltage are researched in detail for the step numbers from 0 to infinity.The critic electric field as the function of the geometry parameters and doping profile is derived.For the thick film device,linear doping profile can be replaced by a single or two steps doping profile in the drift region due to a considerable uniformly lateral electric field,almost ideal breakdown voltage,and simplified design and fabrication.The availability of the proposed model is verified by the good accordance among the analytical results,numerical simulations,and reported experiments.     

均匀、阶梯和线性掺杂漂移区SOI RESURF器件的统一击穿模型

提出了一个均匀、阶梯和线性掺杂漂移区SOI高压器件的统一击穿模型.基于分区求解二维Poisson方程,得到了不同漂移区杂质分布的横向电场和击穿电压的统一解析表达式.借此模型并对阶梯数从0到无穷时器件结构参数对临界电场和击穿电压的影响进行了深入研究.从理论上揭示了在厚膜SOI器件中用阶梯掺杂取代线性漂移区,不但可以保持较高的耐压,而且降低了设计和工艺难度.解析结果、MEDICI仿真结果和实验结果符合良好.     

The frequency response of avalanching photodiodes

The Townsend equations for avalanche breakdown in back biased p-n junctions may be derived from the transport equations for semiconductors. Integral solutions of the time independent equations are well known. An integral solution of the time dependent equations is given for multiplication by one carrier only. An exact solution is given for multiplication by two carriers with equal ionization coefficients in a constant junction field. The Townsend equations are nonlinear because of space charge effects. It is shown, however, that the nonlinearity, which imposes an upper limit on the current multiplication possible, is not important until the total multiplied current approaches the space charge limited current for the junction. Assuming multiplication is due to one carrier, frequency response curves are calculated for constant and linear junction fields and for a generation rate, due to photon absorption, which is either uniform or given by a delta function at the junction boundary. The curves indicate a relatively slight dependence of the frequency response on multiplication. Frequency response curves are also given for multiplication by both carriers with equal ionization coefficients when the junction field is constant. In this case the frequency response decreases continuously as the multiplication is increased. For multiplication by two carriers with unequal ionization coefficients, the frequency response is independent of multiplication until the product of the multiplication and the ratio of the ionization coefficients approaches one. Thereafter the frequency response decreases with multiplication.     

Avalanche multiplication in GaInP/GaAs single heterojunctionbipolar transistors

The electron multiplication factors in GaInP/GaAs single heterojunction bipolar transistors (HBT's) have been measured as a function of base-collector bias for a range of GaAs collector doping densities. In the lowest doped (5×10¹⁴ cm^-3) thick collector the multiplication is determined by the local electric field. As the collector doping increases, the measured multiplication is found to be significantly reduced at low values of multiplication from that predicted by the electric field profile. However, good agreement is always found at high multiplication, close to breakdown. This reduction in multiplication at low electric fields is attributed to the dead space, the minimum distance over which carriers must travel before gaining the ionization threshold energy. A simple correction for the dead space is proposed, allowing the multiplication to be accurately predicted even in heavily doped structures     

高压功率集成电路中LDMOS的设计研究

高压功率集成电路(HVPIC),是指将需要承受高电压(达数百伏)的特定功率晶体管和其它低压的控制电路部分兼容,制作在同一块IC芯片上。本文以器件模拟软件MEDICI为工具,用计算机仿真的方法,研究了一种适用于高压功率集成电路的单晶结构的LDMOS的设计问题,其中包括器件的N阱掺杂浓度、衬底浓度、P反型层浓度和结深等主要参数对击穿电压的影响,重点分析了N阱中P型反型层与漏极N^ 区距离Lp对器件耐压的影响,并分析了相应的物理意义。仿真结果表明,Lp对器件耐压有明显的影响。通过优化设计对应于各个参数器件的击穿电压变高,并且受工艺参数波动影响较小,达到了功率集成电路耐压的要求。     

Breakdown voltage optimization of silicon p-π-v planar junction diodes

Design considerations for optimizing the high-voltage capability of a planar silicon p-π-ν diode structure are studied by computer-aided numerical similation. The effect of varying the π-region width and doping concentration are investigated. An optimum field plate design is determined. The reduction of breakdown voltage due to Qssis calculated. Accurate avalanche breakdown prediction is accomplished by solving the Poisson charge and electron and hole current continuity equations. The values found are a few percent smaller than those obtained by only solving the Poisson equation and then calculating the ionization integral. Discrepancies with previously reported avalanche breakdown calculations and measured data are discussed.     

Breakdown probabilities for thin heterostructure avalanche photodiodes

The recurrence theory for the breakdown probability in avalanche photodiodes (APDs) is generalized to heterostructure APDs that may have multiple multiplication layers. The generalization addresses layer-boundary effects such as the initial energy of injected carriers as well as the layer-dependent profile of the dead space in the multiplication region. Reducing the width of the multiplication layer serves to both downshift and sharpen the breakdown probability curve as a function of the applied reverse-bias voltage. In structures where the injected carriers have an initial energy that is comparable to the ionization threshold energy, the transition from linear mode to Geiger-mode is more abrupt than in structures in which such initial energy is negligible. The theory is applied to two recently fabricated Al/sub 0.6/Ga/sub 0.4/As-GaAs heterostructure APDs and to other homostructure thin GaAs APDs and the predictions of the breakdown-voltage thresholds are verified.     

由等价掺杂转换理论得到非对称线性缓变P-N结的击穿特性

基于等价掺杂转换理论的应用,得到了解析计算非对称线性缓变P-N结击穿特性.由于非对称线性缓变P-N结是单扩散P-N结的一个恰当近似,因而,研究其击穿特性可以更好地理解和设计功率器件P-N结的终端结构.运用等价掺杂转换方法的基本理论得到了不同扩散掺杂梯度和衬底浓度组合系列的击穿电压.研究了最大耗尽层宽度在扩散侧和衬底侧的扩展,给出了它们随扩散掺杂梯度和衬底浓度组合的变化而出现的不同特点.本方法预言的最大击穿电压较之单纯的突变结和对称线性缓变P-N结更接近文献报道的结果,显示了等价掺杂转换理论的理论计算非对称线性缓变P-N结击穿电压的有效性.     

由等价掺杂转换理论得到非对称线性缓变P-N结的击穿特性

基于等价掺杂转换理论的应用,得到了解析计算非对称线性缓变P-N结击穿特性.由于非对称线性缓变P-N结是单扩散P-N结的一个恰当近似,因而,研究其击穿特性可以更好地理解和设计功率器件P-N结的终端结构.运用等价掺杂转换方法的基本理论得到了不同扩散掺杂梯度和衬底浓度组合系列的击穿电压.研究了最大耗尽层宽度在扩散侧和衬底侧的扩展,给出了它们随扩散掺杂梯度和衬底浓度组合的变化而出现的不同特点.本方法预言的最大击穿电压较之单纯的突变结和对称线性缓变P-N结更接近文献报道的结果,显示了等价掺杂转换理论的理论计算非对称线性缓变P-N结击穿电压的有效性.     

Excess gate current analysis of junction gate FET's by two- dimensional computer simulation

Gate current in a JFET under high drain bias is much higher than expected from the classical theory for reverse-biased p-n junctions. This excess gate current is caused by minority carriers generated by low-level impact ionization in the conducting channel, while the so-called breakdown voltage is determined by high-level avalanche multiplication near the gate edge at the surface. A simple one-dimensional model for the excess gate current is proposed. This model is based on the results of two-dimensional numerical analysis, which neglects the minority carrier motion. The excess gate current and avalanche breakdown voltage are calculated from one-dimensional ionization integrals, which are obtained numerically by utilizing the solution of two-dimensional analysis. The reverberant effect of the generated carriers on the potential distribution is assumed to be negligible. The results of the calculation are in good agreement with experimental results, without any adjustable parameters. Moreover, various impurity doping profiles are analyzed for the purpose of minimizing excess gate current. The present model requires a reasonably short computation time and is useful for designing JFET devices.     

SiGe/Si单光子雪崩光电二极管仿真

通过理论模拟CMOS工艺兼容的SiGe/Si 单光子雪崩二极管,研究并讨论了掺杂条件对于电场分布、频宽特性、以及器件量子效率的影响。设计出具有浅结结构、可在盖革模式下工作、低击穿电压(30 V)的1.06 m单光子技术雪崩光电二极管。器件采用分离吸收倍增区结构,其中Si材料作为倍增区、SiGe材料作为吸收区,这充分利用了硅材料较高的载流子离化比差异,降低了器件噪声;在1.06 m波长下,SiGe探测器的量子效率为4.2%,相比于Si探测器的效率提高了4 倍。仿真表明优化掺杂条件可以优化电场分布,从而在APD击穿电压处获得更好的带宽特性。     

Design curves of breakdown voltage at field plate edge and effect of interface charge

Useful design curves of breakdown voltage are provided, which allow determination of breakdown voltage at the field plate edge in terms of field plate length, oxide thickness, and substrate doping concentration. The effect of the interface charge on the breakdown voltage is analyzed and determined also from the curves. The analytical results show a fair agreement with the two-dimensional device simulations using MEDICI as well as with the experimental results reported.     

A physically-based MOS transistor avalanche breakdown model

A physically based breakdown model for MOSFET's is presented to rectify the unexplained experimental breakdown behaviors. The drain avalanche breakdown in the MOS transistor can be caused by either infinite multiplication (MI) or finite multiplication with positive feedback of the substrate current (MF) due to the impact ionization in the pinch-off region. The breakdown voltages of these two modes of breakdown have different dependencies on the biasing conditions and device parameters. For MI mode of breakdown, the breakdown voltage increases slowly with the gate voltage and can be approximated by the drain saturation voltage plus a constant offset. For MF mode of breakdown, the breakdown voltage decreases as the drain saturation current becomes larger. The calculated breakdown characteristics agree well with the measured ones for devices with effective channel length in the range of 0.44~10 μm     

A numerical model of avalanche breakdown in MOSFET's

An accurate numerical model of avalanche breakdown in MOSFET's is presented. Features of this model are a) use of an accurate electric-field distribution calculated by a two-dimensional numerical analysis, b) introduction of multiplication factors for a high-field path and the channel current path, and c) incorporation of the feedback effect of the excess substrate current induced by impact ionization into the two-dimensional calculation. This model is applied to normal breakdown observed in p-MOSFET's and to negative-resistance breakdown (snap-back or switchback breakdown) observed in short-channel n-MOSFET's. Excess substrate current generated from channel current by impact ionization causes a significant voltage drop across the substrate resistance in short-channel n-MOSFET's. This voltage forward-biases the source-substrate junction and increases channel current causing a positive feedback effect. This results in a decrease of the breakdown voltage and leads to negative-resistance characteristics. Current-voltage characteristics calculated by the present model agree very well with experimental results. Another model, highly simplified and convenient for device design, is also presented. It predicts some advantages of p-MOSFET's over n-MOSFET's from the standpoint of avalanche breakdown voltage, particularly in the submicrometer channel-length range.     

Effect of dead space on gain and noise in Si and GaAs avalanchephotodiodes

The effect of dead space on the mean gain, the excess noise factor, and the avalanche breakdown voltage for Si and GaAs avalanche photodiodes (APDs) with nonuniform carrier ionization coefficients are examined. The dead space, which is a function of the electric field and position within the multiplication region of the APD, is the minimum distance that a newly generated carrier must travel in order to acquire sufficient energy to become capable of causing impact ionization. Recurrence relations in the form of coupled linear integral equations are derived to characterize the underlying avalanche multiplication process. Numerical solutions to the integral equations are obtained and the mean gain and the excess noise factor are computed     

Equivalent doping profile transformation: a semi-empirical,analytical method for predicting breakdown characteristics of anapproximate single-diffused parallel-plane junction

In this paper, a semi-empirical analytical method called the equivalent doping profile transformation method (EDPTM) has been proposed for the first time to predict the breakdown characteristics of an approximate single-diffused parallel-plane pn-junction that has a doping profile of the combination of a diffused side linear gradient constant and a constant substrate doping concentration, which considers the influence of the diffusion gradient level on the space charge region of the substrate side. Through the equivalent doping profile transformation, this approximate pn-junction turns into a double-sided asymmetric linear-graded junction (Jin et al., 1999). As a result, the breakdown voltage, critical peak electrical field, and the maximum depletion layer width can be carefully evaluated at different doping substrate concentration and gradient constant combinations. Compared with previous approximations such as abrupt and classical symmetrical linear-graded junctions, this method can give exact breakdown characteristics of a single-diffused pn-junction. The results are in excellent agreement with the numerical analysis, which proves the validity of this new method     

Deep-implant 1-µm MOSFET structure with improved threshold control for VLSI circuitry

MOSFET structures with an optimized doping profile show improved threshold control and subthreshold performance. This is achieved by a low-dose shallow implant defining the level of the threshold and a higher dose deep implant improving short-channel effects like SDIBL and VDIBL. Besides surface and volume barrier lowering, body effect, parasitic capacitance, avalanche multiplication, and breakdown voltage have been investigated. In spite of the increased substrate sensitivity and junction capacitances, the deep-implant concept only provides transistors with reasonable terminal characteristics in the 1-µm and submicrometer range.