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 共查询到18条相似文献,搜索用时 171 毫秒
1.
A low reset noise CMOS image sensor(CIS) based on column-level feedback reset is proposed.A feedback loop was formed through an amplifier and a switch.A prototype CMOS image sensor was developed with a 0.18μm CIS process.Through matching the noise bandwidth and the bandwidth of the amplifier,with the falling time period of the reset impulse 6μs,experimental results show the reset noise level can experience up to 25 dB reduction.The proposed CMOS image sensor meets the demand of applications in high speed security surveillance systems,especially in low illumination.  相似文献   

2.
A FPGA-based image recognition system is designed for eolorimetric sensor array in order to recognize a wide range of volatile organic compounds. The gas molecule is detected by the responsive sensor array and the responsive image is obtained. The image is decomposed to RGB color components using CMOS image sensor. An embedded image recognition archi- tecture based on Xilinx Spartan-3 FPGA is designed to implement the algorithms of image recognition. The algorithm of color coherence vector is discussed in detail compared with the algorithm of color histograms, and experimental results demonstrate that both of the two algorithms could be analyzed effectively to represent different volatile organic compounds according to their different responsive images in this system.  相似文献   

3.
应用于高速CMOS图像传感器的10比特列并行循环式ADC   总被引:1,自引:1,他引:0  
韩烨  李全良  石匆  吴南健 《半导体学报》2013,34(8):085016-6
This paper presents a high-speed column-parallel cyclic analog-to-digital converter(ADC) for a CMOS image sensor.A correlated double sampling(CDS) circuit is integrated in the ADC,which avoids a stand-alone CDS circuit block.An offset cancellation technique is also introduced,which reduces the column fixed-pattern noise(FPN) effectively.One single channel ADC with an area less than 0.02 mm~2 was implemented in a 0.13μm CMOS image sensor process.The resolution of the proposed ADC is 10-bit,and the conversion rate is 1.6 MS/s. The measured differential nonlinearity and integral nonlinearity are 0.89 LSB and 6.2 LSB together with CDS, respectively.The power consumption from 3.3 V supply is only 0.66 mW.An array of 48 10-bit column-parallel cyclic ADCs was integrated into an array of CMOS image sensor pixels.The measured results indicated that the ADC circuit is suitable for high-speed CMOS image sensors.  相似文献   

4.
李贵柯  冯鹏  吴南健 《半导体学报》2011,32(10):133-138
We present a monolithic ultraviolet(UV) image sensor based on a standard CMOS process.A compact UV sensitive device structure is designed as a pixel for the image sensor.This UV image sensor consists of a CMOS pixel array,high-voltage switches,a readout circuit and a digital control circuit.A 16×16 image sensor prototype chip is implemented in a 0.18μm standard CMOS logic process.The pixel and image sensor were measured. Experimental results demonstrate that the image sensor has a high sensitivity of 0.072 V/(mJ/cm~2) and can capture a UV image.It is suitable for large-scale monolithic bio-medical and space applications.  相似文献   

5.
A single Complementary Metal Oxide Semiconductor (CMOS) image sensor based on 0.35 μm process along with its design and implementation is introduced in this paper. The pixel architecture of Active Pixel Sensor (APS) is used in the chip, which comprises a 256×256 pixel array together with column amplifiers, scan array circuits, series interface, control logic and Analog-Digital Converter (ADC). With the use of smart layout design, fill factor of pixel cell is 43%. Moreover, a new method of Dynamic Digital Double Sample (DDDS) which removes Fixed Pattern Noise (FPN) is used.The CMOS image sensor chip is implemented based on the 0.35 μm process of chartered by Multi-Project Wafer (MPW). This chip performs well as expected.  相似文献   

6.
To overcome the limitation of low image signal swing range and long reset time in four Iransistor CMOS active pixel image sensor, a charge pump circuit is presented to improve the pixel reset performance. The charge pump circuit consists of two stage switch capacitor serial voltage doubler. Cross-coupled MOSFET switch structure with well close and open performance is used in the second stage of the charge pump. The pixel reset transistor with gate voltage driven by output of the pump works in linear region, which can accelerate reset process and complete reset is achieved. The simulation results show that output of the charge pump is enhanced from 1.2 to 4.2 V with voltage ripple lower than 6 inV. The pixel reset time is reduced to 1.14 ns in dark. Image smear due to non-completely reset is elIminated and the image signal swing range is enlarged. The charge pump is successfully embedded in a CMOS image sensor chip with 0.3 × 10^6 pixels.  相似文献   

7.
An approach to obtain the pinch-off voltage of 4-T pixel in CMOS image sensor is presented.This new approach is based on the assumption that the photon shot noise in image signal is impacted by a potential well structure change of pixel.Experimental results show the measured pinch-off voltage is consistent with theoretical prediction.This technique provides an experimental method to assist the optimization of pixel design in both the photodiode structure and fabrication process for the 4-T CMOS image sen...  相似文献   

8.
The principle of the two carriers contributing to carry the pixel signal charges is firstly presented,and then the bipolar junction photogate transistor(BJPT)with high performance is proposed for the CMOS image sensor.The numerical analytical model of the photo-Chrge transfer for the bipolar junction photogate is established in detail.Some numerical simulations are obtained unider 0.6μm CMOS process,which show that its readout rate increases exponentially with the increase of the photo-Charge at applied voltage.  相似文献   

9.
With the scaling development of the minimum lithographic size, the scaling trend of CMOS imager pixel size and fill factor has been computed according to the Moore rule. When the CMOS minimum lithographic feature scales down to 0.35 μm,the CCD imagepixel size is not so easy to be reduced and but the CMOS image pixel size benefits from the scaling minimum lithographic feature. However, when the CMOS technology is downscaled to or under 0.35μm,the fabrication of CMOS image sensors will be limited by the standard CMOS process in both ways of shallow trench isolation and source/drain junction, which results in pixel crosstalk. The impact of the crosstalk on the active pixel CMOS image sensor is analyzed based on the technology scaling. Some suppressed crosstalk methods have been reviewed. The best way is that combining the advantages of CMOS and SOI technology to fabricate the image sensors will reduce the pixel crosstalk.  相似文献   

10.
Presented was an optimum designed CMOS active pixel sensor. In this sensor, used is a PMOSFET substituting for the NMOSFET in traditional sensor as restoration transistor. Compared with traditional active pixel sensor under the same condition based on 0.25 μm CMOS technology, simulating results show that the new structure device has higher signal-to-noise ratio, wider output swing, wider dynamic range and faster readout speed.  相似文献   

11.
A high speed analog VLSI image acquisition and low-level image processing system is presented. The architecture of the chip is based on a dynamically reconfigurable SIMD processor array. The chip features a massively parallel architecture enabling the computation of programmable mask-based image processing in each pixel. Each pixel include a photodiode, an amplifier, two storage capacitors, and an analog arithmetic unit based on a four-quadrant multiplier architecture. A 64 × 64 pixel proof-of-concept chip was fabricated in a 0.35 μm standard CMOS process, with a pixel size of 35 μm × 35 μm. The chip can capture raw images up to 10,000 fps and runs low-level image processing at a framerate of 2,000–5,000 fps.  相似文献   

12.
介绍了基于0.35μm工艺设计的单片CMOS图像传感器芯片.该芯片采用有源像素结构,像素单元填充因数可达到43%,高于通常APS结构像素单元30%的指标.此外还设计了一种数字动态双采样技术,相对于传统的双采样技术(固定模式噪声约为0.5%),数字动态双采样技术具有更简洁的电路结构和更好抑制FPN噪声的效果.传感器芯片通过MPW计划采用Chartered 0.35μm数模混合工艺实现.实验结果表明芯片工作良好,图像固定模式噪声约为0.17%.  相似文献   

13.
This paper presents a 256×256 pixel smart CMOS image sensor for line based vision applications. By combining the edge-based analog processing technique with an active pixel array, a dense and fast on-chip analog image processing has been achieved. The on-chip processing unit includes (1) an analog histogram equalizer, (2) a programmable recursive Gaussian filter, (3) a spatio-temporal differentiator, and (4) a local extrema extractor. An electronic shutter is applied to the active pixel sensor array in order to adapt the exposure time as a function of global illumination. The on-chip histogram equalizer extends the image into a constant and optimal range for all the following processing operators and gives a stable and predictable precision of the analog processing. A prototype chip has been designed and fabricated in a standard 0.8-μm CMOS process with double poly and double metal, giving a pixel pitch of 20 μm and die size of 7×7 mm2. A line processing time is compatible with TV line scan period. The worst case power consumption measures 40 mA at 5 V  相似文献   

14.
CMOS图像传感器固定模式噪声抑制新技术。   总被引:1,自引:0,他引:1  
针对有源像素(APS)CMOS图像传感器中的固定模式噪声(FPN),设计了一种动态数字双采样的噪声抑制新技术;该技术比普通双采样技术具有更佳的抑制效果,其电路结构简单,适合于像素尺寸不断缩小的CMOS图像传感器发展趋势。通过MPW计划,采用Chartered0.35μmCMOS工艺制作了测试ASIC芯片,试验结果表明动态数字双采样技术有效抑制了FPN噪声。  相似文献   

15.
设计了一种基于电容反馈跨阻放大器(CTIA)的长线列CMOS图像传感器。为减小器件功耗和面积,采用基于单端四管共源共栅运算放大器。为提高信号读出速率,采用没有体效应的PMOS源跟随器,同时减小PMOS管的宽长比,有效减小了输出总线寄生电容的影响。在版图设计上,采用顶层金属走线,降低寄生电阻和电容,提高了长线列CMOS图像传感器的读出速率和输出线性范围。采用0.35μm 3.3V标准CMOS工艺对传感器进行流片,得到器件像元阵列为5×1 030,像元尺寸为20μm×20μm。测试结果表明:该传感器在积分时间为1ms、读出速率为4MHz的情况下工作稳定,其线性度达到98%,线性动态范围为76dB。  相似文献   

16.
We have constructed an addressable 256 × 256 photodiode sensor array together with an 8-bit ADC (analog-to-digital converter) on the same chip. Such a digital camera is easy to connect to a computer where also the flexibility of the computer can be used to control the camera output. The sensor has been constructed in two versions. The first version was implemented with a 256-column parallel-bit-slice image processor on the same die in a commercial project and the second as a separate addressable digital image sensor. The sensor was functionally fabricated using 1.6 µm design rules in a 1.2 µm CMOS process where it required a total area of 96 mm2.  相似文献   

17.
A technical investigation, research and im-plementation is presented to correct column fixed pattern noise and black level in large array Complementary metal oxide semiconductor (CMOS) image sensor. Through making a comparison among reported solution, and give large array CMOS image sensor design and considerations, according to our previous analysis on non-ideal factor and error source of piecewise Digital to analog converter (DAC) in multi-channels, an improving accurate piecewise DAC with adaptive switch technique is developed. The research theory has verified by a high dynamic range and low column Fixed pattern noise (FPN) CMOS image sensor prototype chip, which consisting of 8320×8320 pixel array was designed and fabricated in 55nm CMOS 1P4M standard process. The chip active area is 48mm×48mm with a pixel size of 5.7μm×5.7μm. The measured results achieved a high intrinsic dynamic range of 75dB, a low FPN and black level of 0.06%, a low photo response non-uniformity of 1.5% respectively, and an excellent raw sample image taken by the prototype sensor.  相似文献   

18.
This article presents a small-area, ultra low-power, low-mismatch differencing transient amplifier for ROIC pixels of micro-bolometer based temporal contrast IR sensors. The two-stage capacitive-feedback amplifier works in the sub-threshold domain, has a voltage gain of 46 dB, a 3 dB bandwidth of about 10 kHz and consumes 85 nW of static power. The amplifier circuit has been fabricated in a 0.35 μm standard CMOS process and consumes less than 2000 μm2 of silicon area, enabling a square pixel size of 50 × 50 μm for the IR sensor array.  相似文献   

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