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提出一种基于渐进边增长(Progressive Edge.Growth,PEG)算法的非规则全分集低密度奇偶校验(Low—Density Parity—Check,LDPC)码的构造方法。首先根据度分布和码率,对非规则全分集LDPC码中的节点进行度分配;然后对PEG算法中校验节点的选择标准加以约束,生成消除短环的非规则全分集LDPC码;进一步,通过改变局部校验节点剩余度的方法,解决在特殊度分布下算法失效的问题。仿真结果表明,构造的非规则全分集LDPC码在瑞利块衰落信道下能够实现全分集;在码长、码率相同的情况下与规则全分集LDPC码相比,非规则全分集LD—PC码能够获得更高的编码增益。 相似文献
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文中硬件实现了一种非规则的低密度奇偶校验码在一定的约束条件下,利用具有一定结构的校验矩阵来降低编码复杂度的LDPC码,并给出了编码器设计实现原理、结构和基本组成。在Quartus 9.0软件平台上采用基于FPGA的Verilog硬件描述语言,在Altera的Cyclone系列型号为EP1C6Q240C8N的芯片硬件平台实现了整个编码过程中所有模块的功能,并通过Matlab验证了编码结果的正确性。同时,该编码方案还可灵活应用于不同码长的系统中。 相似文献
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广义低密度奇偶校验(Generalized Low睤ensity Parity睠heck,GLDPC)码把低密度奇偶校验(Low睤ensity Parity睠heck,LDPC)码中的单奇偶校验(Single Parity睠heck,SPC)节点替换为校验能力更强的广义约束(Generalized Constraint,GC)节点,使其在中短码和低码率的条件下具有更低的误码率。传统GLDPC码要求基矩阵的行重等于分量码的码长,这限制了GLDPC码构造的灵活性。另外,相比于传统GLDPC码中GC节点位置的随机选取,GC节点的位置选择在GLDPC码的误码率性能上有一定的优化空间。针对以上两点,提出了一种基于渐进边增长(Progressive Edge-rowth,PEG)算法的非规则GLDPC码构造方法和一种基于Tanner图边数的GC节点位置选择算法。使用PEG算法生成的非规则LDPC码作为本地码,根据本地码的校验节点度使用多种分量码,结合GC节点位置选择算法构造非规则GLDPC码。仿真结果表明,与传统方法构造的GLDPC码相比,基于Tanner图边数的GC节点位置选择算法构造的非规则PEG-LDPC码在误码率和译码复杂度上均得到明显改善。 相似文献
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LDPC码性能非常逼近香农极限且实现复杂度低,具有很强的纠错抗干扰能力,几乎适用于所有信道。在此采用DVB-S2标准中LDPC码的构造和编码方案,重点研究了LDPC码的译码原理,并将其用于加性高斯白噪声信道(AWGN Channel)图像的传输中。仿真结果表明在非规则LDPC码在低信噪比情况下,能为图像传输带来显著性能提高,且系统复杂度低,译码时延短。 相似文献
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Array—LDPC码是一种高码率的LDPC(低密度奇偶校验)码,具有高性能、易编码等特点,广泛应用于DSL(数字用户线)传输中。在分析ArrayLDPC码结构和MS(最小和)算法的基础上,提出一种在较低硬件复杂度下实现较高并行度的解码器架构。该架构显著降低了节点间的信息通信量,同时,用局部CPU之间有规律的信息传递取代了VPU与CPU之间复杂的信息交换,解决了硬件实现中的布线问题。设计结果表明,采用这种架构设计的(2209,2021)Array.LDPC解码器具有吞吐率高、结构简单的优点,在0.18μmCMOS工艺下,面积仅为2.4mm2,而吞吐率可达到1.03Gbps。 相似文献
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随着LDPC码的广泛应用,尤其是在电池供电设备上的应用,解码器设计者面临的一个重大挑战就是如何减少其使用的存储器大小和存储器块数.行消息传递算法和基于置信传播的归一化算法的提出使得设计存储器的优化的解码器更为容易.对于一个普通的规则LDPC码来说,则存在一种性能良好且节省存储器的串行解码器结构,一个针对David MacKay的4000×8000规则LDPC码的解码器设计就是一个很好的例子. 相似文献
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提出了一种基于WiMax 802.16e标准的LDPC码解码器结构,该结构采用了基于修正的SP算法的串并行结构,支持19种协议规定的校验矩阵及码字长度,以及六种不同码率的LDPC码的解码,并在是否使用分层解码两种情况下进行了仿真验证,降低了解码延时和误码率. 相似文献
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《Microelectronics Journal》2014,45(11):1489-1498
In this paper, an area efficient and high throughput multi-rate quasi-cyclic low-density parity-check (QC-LDPC) decoder for IEEE 802.11n applications is proposed. An overlapped message passing scheme and the non-uniform quantization scheme are incorporated to reduce the overall area and power of the proposed QC-LDPC decoder. In order to enhance the decoding throughput and reduce the size of memories storing soft messages, an improved early termination (ET) scheme and base matrix reordering technique is employed. These techniques significantly reduce the total number of decoding iterations and memory accessing conflicts without mitigating the decoding performance. Equipped with these techniques an area efficient and high throughput multi-rate QC-LDPC decoder is designed, simulated and implemented with Xilinx Virtex6 (XC6VLX760-2FF1760) for an irregular LDPC code of length 1944 and code rates (1/2–5/6) specified in IEEE 802.11n standard. With a maximum clock frequency of 574.136–587.458 MHz the proposed QC-LDPC decoder can achieve throughput in the range of 1.27–2.17 Gb/s for 10 decoding iterations. Furthermore, by using Cadence RTL compiler with UMC 130 nm VLSI technology, the core area of the proposed QC-LDPC decoder is found to be 1.42 mm2 with a power dissipation in the range of 101.25–140.42 mW at 1.2 V supply voltage. 相似文献
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Although Low-Density Parity-Check (LDPC) codes perform admirably for large block sizes — being mostly resilient to low levels of channel SNR and errors in channel equalization — real time operation and low computational effort require small and medium sized codes, which tend to be affected by these two factors. For these small to medium codes, a method for designing efficient regular codes is presented and a new technique for reducing the dependency of correct channel equalization, without much change in the inner workings or architecture of existing LDPC decoders is proposed. This goal is achieved by an improved intrinsic Log-Likelihood Ratio (LLR) estimator in the LDPC decoder — the ILE-Decoder, which only uses LDPC decoder-side information gathered during standard LDPC decoding. This information is used to improve the channel parameters estimation, thus improving the reliability of the code correction, while reducing the number of required iterations for a successful decoding. Methods for fast encoding and decoding of LDPC codes are presented, highlighting the importance of assuring low encoding/decoding latency with maintaining high throughput. The assumptions and rules that govern the estimation process via subcarrier corrected-bit accounting are presented, and the Bayesian inference estimation process is detailed. This scheme is suitable for application to multicarrier communications, such as OFDM. Simulation results in a PLC-like environment that confirm the good performance of the proposed LDPC coder/decoder are presented. 相似文献
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由于传统的LLR BP译码算法不易于FPGA实现,为了降低实现复杂度,采用一种改进的LLR BP译码实现方法,设计了一种码长为40、码率为0.5的规则LDPC码译码器,并完成了FPGA仿真实现.仿真和综合的结果表明,所设计的译码器吞吐量达到15.68 Mbit/s,且译码器的资源消耗适中. 相似文献
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Low-density parity-check (LDPC) codes, proposed by Gallager, emerged as a class of codes which can yield very good performance on the additive white Gaussian noise channel as well as on the binary symmetric channel. LDPC codes have gained lots of importance due to their capacity achieving property and excellent performance in the noisy channel. Belief propagation (BP) algorithm and its approximations, most notably min-sum, are popular iterative decoding algorithms used for LDPC and turbo codes. The trade-off between the hardware complexity and the decoding throughput is a critical factor in the implementation of the practical decoder. This article presents introduction to LDPC codes and its various decoding algorithms followed by realisation of LDPC decoder by using simplified message passing algorithm and partially parallel decoder architecture. Simplified message passing algorithm has been proposed for trade-off between low decoding complexity and decoder performance. It greatly reduces the routing and check node complexity of the decoder. Partially parallel decoder architecture possesses high speed and reduced complexity. The improved design of the decoder possesses a maximum symbol throughput of 92.95 Mbps and a maximum of 18 decoding iterations. The article presents implementation of 9216 bits, rate-1/2, (3, 6) LDPC decoder on Xilinx XC3D3400A device from Spartan-3A DSP family. 相似文献
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本论文用可编程逻辑器件(FPGA)实现了一种低密度奇偶校验码(LDPC)的编译码算法.采用基于Q矩阵LDPC码构造方法,设计了具有线性复杂度的编码器. 基于软判决译码规则,采用全并行译码结构实现了码率为1/2、码长为40比特的准规则LDPC码译码器,并且通过了仿真测试.该译码器复杂度与码长成线性关系,与Turbo码相比更易于硬件实现,并能达到更高的传输速率. 相似文献
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提出了一种兼容Turbo码的低密度校验码(LDPC)解码器,它可以将Turbo码完全转化为LDPC码来进行解码,由于采用了校验分裂方法来处理由Turbo码转化而来的LDPC码中所存在的短环,从而使其解码性能优于联合校验置信度传递(JCBP)算法0.8 dB,仅仅比Turbo码专用的BCJR算法损失约为1dB.本文提出的通用解码器,为多系统兼容通信设备的应用提供了一种新的、灵活方便的实现途径. 相似文献