Feasibility of BCB as an interlevel dielectric in integrated circuits

This paper investigates the feasibility of using an organic polymer based on benzocyclobutene as an interlevel dielectric material in very large scale integrated (VLSI) circuits. The material is a thermoset resin with attractive electrical and mechanical properties for application as an interlevel dielectric in VLSI circuits. It has a low relative dielectric constant of 2.7. The single coating planarization achieved by spin coating the material is superior to currently used materials and makes it a very attractive material for the fabrication of multilevel metal systems. The planarization properties of this material are presented and compared with those of polyimide. The patterning and dry etching of BCB to define 1 μm vias is described. As the material has limited thermal stability at temperatures greater than 350°C, compatible materials for low via resistivity have been investigated using a double level metal structure. The effect of post metal anneals on via resistivity of various via structures is presented. It is found that a low via resistivity of 3 × 10^-9 gW-cm² without any post metal anneal is obtained by using an AlCu/Pd-AlCu metallurgy.     

异步集成电路设计的研究与进展

回顾了异步集成电路设计发展的历史,阐述了当前异步集成电路重新引起重视的原因,总结了异步集成电路的优势,并对异步集成电路设计方法进行了简要地概括,介绍了实用的异步集成电路芯片,最后分析了异步集成电路面临的挑战,并揭示了它今后的发展方向.     

Hybrid material integration in silicon photonic integrated circuits

Hybrid integration ofⅢ-Ⅴand ferroelectric materials is being broadly adopted to enhance functionalities in silicon photonic integrated circuits(PICs).Bonding and transfer printing have been the popular approaches for integration of III–V gain media with silicon PICs.Similar approaches are also being considered for ferroelectrics to enable larger RF modulation bandwidths,higher linearity,lower optical loss integrated optical modulators on chip.In this paper,we review existing integration strategies ofⅢ-Ⅴmaterials and present a route towards hybrid integration of bothⅢ-Ⅴand ferroelectrics on the same chip.We show that adiabatic transformation of the optical mode between hybrid ferroelectric and silicon sections enables efficient transfer of optical modal energies for maximum overlap of the optical mode with the ferroelectric media,similar to approaches adopted to maximize optical overlap with the gain section,thereby reducing lasing thresholds for hybridⅢ-Ⅴintegration with silicon PICs.Preliminary designs are presented to enable a foundry compatible hybrid integration route of diverse functionalities on silicon PICs.     

Epitaxial spinel growth for integrated circuits

This is a report on our investigation of the epitaxial growth of Si-on-spinel-on-Si double-heterostructure integrated circuit material. The spinel epitaxial layers were grown on the Si substrate with an open-tube Al-HCl-MgCl₂-CO₂H₂ VPE system. High electron Hall-mobility and low defect density in the active Si layers were achieved with optimum growth conditions for spinel and silicon. Bipolar transistors, MOS devices and high-voltage bipolar ICs were fabricated in the active Si layers on epitaxially grown spinel.     

TRANSIENT CHARACTERISTIC ANALYSIS OF HIGH TEMPERATURE CMOS DIGITAL INTEGRATED CIRCUITS

This paper analyses the transient characteristics of high temperature CMOS inverters and gate circuits, and gives the computational formulas of their rise time, fall time and delay time. It may be concluded that the transient characteristics of CMOS inverters and gate circuits deteriorate due to the reduction of carrier mobilities and threshold voltages of MOS transistors and the increase of leakage currents of MOS transistors drain terminal pn junctions. The calculation results can explain the experimental phenomenon.     

Progress in complementary metal-oxide-semiconductor silicon photonics and optoelectronic integrated circuits

Silicon photonics is an emerging competitive solution for next-generation scalable data communications in different application areas as high-speed data communication is constrained by electrical interconnects. Optical interconnects based on silicon photonics can be used in intra/inter-chip interconnects, board-to-board interconnects, short-reach communications in datacenters, supercomputers and long-haul optical transmissions. In this paper, we present an overview of recent progress in silicon optoelectronic devices and optoelectronic integrated circuits(OEICs) based on a complementary metal-oxide-semiconductor-compatible process, and focus on our research contributions. The silicon optoelectronic devices and OEICs show good characteristics, which are expected to benefit several application domains, including communication, sensing, computing and nonlinear systems.     

一种基于数值积分的集成电路成品率估计方法

本文提出了一种基于数值积分的集成电路成品率估计方法。该方法通过直接在可接受域上对性能的联合概率密度函数进行积分获得成品率的估计。为达到此目的,性能的仿真数据须先经由Box-Cox变换 (BCT) 转化为服从多变量正态分布的数据。同时,文中采用了基于正交表的改进拉丁超立方体抽样法 (OA-MLHS) 对电路的工艺扰动参数实施抽样,如此可以大幅减小联合概率密度函数中分布参数的估计方差。文中对结合使用OA-MLHS与BCT从而减少了分布参数的估计方差的数学原理进行了分析。以一个四阶OTA-C低通滤波器和一个三维二次函数的成品率估计为例,在不同的样本量及成品率水平的组合下,对包含拉丁超立方体抽样和重要抽样等的六种不同的成品率估计法做了性能比较。大量的仿真证明本文所述的方法无论在精度还是效率上都要优于其他几种方法。因此,该方法更加适用于集成电路的成品率优化。     

A numerical integration-based yield estimation method for integrated circuits

A novel integration-based yield estimation method is developed for yield optimization of integrated circuits.This method tries to integrate the joint probability density function on the acceptability region directly. To achieve this goal,the simulated performance data of unknown distribution should be converted to follow a multivariate normal distribution by using Box-Cox transformation(BCT).In order to reduce the estimation variances of the model parameters of the density function,orthogonal array-based modified Latin hypercube sampling (OA-MLHS) is presented to generate samples in the disturbance space during simulations.The principle of variance reduction of model parameters estimation through OA-MLHS together with BCT is also discussed.Two yield estimation examples,a fourth-order OTA-C filter and a three-dimensional(3D) quadratic function are used for comparison of our method with Monte Carlo based methods including Latin hypercube sampling and importance sampling under several combinations of sample sizes and yield values.Extensive simulations show that our method is superior to other methods with respect to accuracy and efficiency under all of the given cases.Therefore,our method is more suitable for parametric yield optimization.     

基于专用控制芯片的步进电机运动控制系统设计

为了降低研发成本,减轻微控制器的压力,提高系统的稳定性和灵活性,提出了一种基于专用控制芯片的步进电机运动控制系统设计方案。该运动控制系统中主要采用了微控制器AT90CAN128、步进电机驱动芯片TMC262和步进电机运动控制芯片TMC429。一旦初始化,系统可同时控制3个两相步进电机,并且可自主完成各种实时关键任务。测试结果表明所设计的控制系统具有数据传输稳定、性价比高、易于控制等优点,达到了预期的设计效果和要求。     

Ground bounce modelling for digital gigascale integrated circuits

In the paper, an analytical model for ground bounce noise evaluation taking into account the interdependence between I_DD switching current and V_DD noise voltage is presented. The model shows the discrepancies from general accepted assumption of independence between the two variables. The main conclusion is that noise calculations using the independence assumption cause an overestimation of the noise levels. The results are verified through realistic simulations and for different technology nodes and accurate analysis of two canonical circuits.     

Electrical characterization of analogue and RF integrated circuits by thermal measurements

This paper presents a novel technique for measuring the electrical characteristics of analogue circuits, based on measuring the temperature at the silicon surface close to the circuit under test. As a detailed example, the paper analyses how the gain of an amplifier can be observed through temperature measurements. Experimental results validate the feasibility of the technique. Simulated results show how this technique can be used to measure the bandwidth and central frequency of a 2.4 GHz low noise amplifier (LNA) designed in a 0.35 μm standard CMOS technology.     

集成电路的可靠性再筛选

本文介绍了器件可靠性筛选在集成电路生产过程和工艺生产上的重要性，提出了器件可造性筛选的一些重要方法。     

A design for testability approach for nano-CMOS analogue integrated circuits

Dependability requirements must be considered from the beginning when designing safety-critical systems. Therefore, testing should even be considered earlier, intertwined with the design process. The process of designing for better testability is called design for testability (DfT). This article presents two designs for testability and fault diagnosis techniques using a new design analogue checker circuit in order to improve the testability and the diagnosability of nano-CMOS (complementary metal oxide semiconductor) analogue circuits used in safety-critical applications based on the system-on-chip (SoC) approach design. The testing techniques presented in this work can be done during and after the system fabrication. The checker is implemented in full-custom 65 nm Complementary metal–oxide–semiconductor (CMOS) technology with low supply voltage and small-size capabilities. SPICE simulations of the post-layout extracted CMOS checker, which include all parasitic, are used to validate the technique and demonstrate the acceptable electrical behaviour of the checker.     

器件参数宏模型的精确建立及其在模拟集成电路性能建模与优化中的应用

Techniques for constructing metamodels of device parameters at BSIM3v3 level accuracy are presented to improve knowledge-based circuit sizing optimization. Based on the analysis of the prediction error of analytical performance expressions, operating point driven （OPD） metamodels of MOSFETs are introduced to capture the circuit＇s characteristics precisely. In the algorithm of metamodel construction, radial basis functions are adopted to interpolate the scattered multivariate data obtained from a well tailored data sampling scheme designed for MOSFETs. The OPD metamodels can be used to automatically bias the circuit at a specific DC operating point. Analytical-based performance expressions composed by the OPD metamodels show obvious improvement for most small-signal performances compared with simulation-based models. Both operating-point variables and transistor dimensions can be optimized in our nesting-loop optimization formulation to maximize design flexibility. The method is successfully applied to a low-voltage low-power amplifier.     

Accurate metamodels of device parameters and their applications in performance modeling and optimization of analog integrated circuits

Techniques for constructing metamodels of device parameters at BSIM3v3 level accuracy are presnted to improve knowledge-based circuit sizing optimization. Based on the analysis of the prediction error of analytical performance expressions, operating point driven (OPD) metamodels of MOSFETs are introduced to capture the circuit's characteristics precisely. In the algorithm of metamodel construction, radial basis functions are adopted to interpolate the scattered multivariate data obtained from a well tailored data sampling scheme designed for MOSFETs.The OPD metamodels can be used to automatically bias the circuit at a specific DC operating point. Analytical-based performance expressions composed by the OPD metamodels show obvious improvement for most small-signal performances compared with simulation-based models. Both operating-point variables and transistor dimensions can be optimized in our nesting-loop optimization formulation to maximize design flexibility. The method is successfully applied to a low-voltage low-power amplifier.     

Wafer-level three-dimensional integrated circuits (3D IC): Schemes and key technologies

Schemes and key technologies of wafer-level three-dimensional integrated circuits (3D IC) are reviewed and introduced in this paper. Direction of wafer stacking, methods of wafer bonding, fabrication of through-silicon via (TSV), and classification of wafer type are options for 3D IC schemes. Key technologies, such as alignment, Cu bonding, and TSV fabrication, are described as well. Better performance, lower cost, and more functionality of future electronic products become feasible with 3D IC concept application.     

Moisture absorption studies of fluorocarbon films deposited from pentafluoroethane and octafluorocyclobutane plasmas

The moisture absorption and diffusion characteristics of fluorocarbon films deposited from pentafluoroethane (PFE) and octafluorocyclobutane C₄F₈ plasmas are presented. The moisture absorption studies were carried out using a quartz crystal microbalance in a controlled environment. X-ray photoelectron spectroscopy and Fourier transform infrared (IR) spectroscopy were used to monitor the changes in bulk and surface chemical structure and composition of the deposited films. The equilibrium moisture uptake at relative humidity >90% was lower than 0.13 wt.% for films deposited from PFE or C₄F₈ monomers. Humidity cycling measurements showed no moisture chemisorption in the deposited films. Attenuated total reflectance infrared spectroscopy (ATR-IR) spectra of the deposited films indicated negligible change in the bulk composition of the deposited films. The estimated diffusivities of water in the deposited fluorocarbon films were of the order of 10⁻¹⁰ cm²/sec, and films deposited from C₄F₈ monomer showed higher diffusivity as compared to films deposited from PFE monomer. The equilibrium moisture uptake is affected by the presence of polar groups, the F/C ratio, and the O/C ratio. The relatively high diffusivity of water in the fluorocarbon films is attributed to the lack of polar groups in the deposited films. Adsorption onto the surface followed by diffusion into the bulk is proposed as the mechanism for moisture absorption in the fluorocarbon films. Finally, the moisture uptake of the fluorocarbon and hydrofluorocarbon films is compared to that of a conventionally used microelectronic polymer, polyimide (PI 2611), in order to evaluate the effect of polar groups and fluorine content on diffusion and equilibrium moisture uptake.     

High-efficiency bipolar transconductors composed of hyperbolic function circuits with an intermediate voltage terminal and a triple-tail cell

Relatively high transconductance in bipolar devices contributes to the economy of power dissipation on analog integrated circuits. Recently, a high-speed transistor, such as the HBT attracts attention of researchers and developers in electronic communication industries and is expected to be applied to RF circuits. In this paper, high-efficiency bipolar transconductors are presented. The proposed circuits are composed of a hyperbolic function circuit with an intermediate voltage terminal and a triple-tail cell. The parameter values for linearisation are all integers. The values can be realised precisely. The linearity of the proposed transconductors is superior to the triple-tail cell. The linear input range is 1.5 times as wide as that of the conventional triple-tail cell. Nevertheless, the power dissipation is lower than the triple-tail cell. Further, sensitivity analysis shows that the proposed transconductors have lower sensitivity than the triple-tail cell. These properties are confirmed by SPICE simulation.     

Structural and electrical characterization of CoNiO monolayer as copper diffusion barrier in integrated circuits

Diffusion barrier properties of CoNiO monolayer, deposited by Langmuir Blodgett (LB) technique, were studied against the diffusion of copper through SiO₂. Cu/CoNiO/SiO₂/Si and Cu/SiO₂/Si test structures were prepared and compared for this purpose. These test structures were annealed at temperatures starting from 100 °C up to 650 °C in vacuum. Samples were characterized using Energy Dispersive X-ray Spectroscopy (EDS), Atomic force microscopy (AFM), X-ray diffraction (XRD), scanning electron microscope (SEM), four probe resistivity measurement, Capacitance-Voltage (C‒V), Current-Voltage (I‒V) characterization techniques. EDS and AFM confirmed the composition and structure of the deposited monolayer. Thermal stability was studied using X-ray diffraction (XRD), Scanning Electron Microscope (SEM) and four probe techniques. Results indicated that structure with barrier was stable up to 600 °C whereas its counterpart could sustain only up to 300 °C. Sheet resistance of Cu/SiO₂/Si structure starts increasing at 300 °C and that of Cu/CoNiO/SiO₂/Si test structure was almost unchanged up to 600 °C in. SEM analysis of samples annealed at different temperatures also confirmed the XRD and four probe results. Biased Thermal Stress (BTS) was applied to the samples and its effect was observed using C‒V analysis. C‒V curves showed that in the presence of CoNiO barrier layer there was no shift in the C‒V curve even after 120 min of BTS while in the absence of barrier there was a significant shift in the C‒V curve even after 30 min of BTS. Leakage current density (j_L) was plotted against the BTS duration under same BTS conditions. It was found that the Cu/CoNiO/SiO₂/Si stack could survive about two times more than the Cu/SiO₂/Si stack.     

聚酰亚胺衬底中双频段太赫兹异向介质特性研究

将两种不同结构的异向介质同时嵌在聚酰亚胺衬底中,在太赫兹波段实现了两个不同的谐振频率响应。分析了不同衬底厚度对谐振特性的影响。结果表明,当衬底厚度为30μm时,两个结构会相互影响,从而使谐振幅度和谐振频率有所改变;当衬底厚度增加到100μm时,两个谐振点谐振特性彼此独立,互不影响。