Thermal cycling-induced changes in excess dark current in very long-wavelength HgCdTe photodiodes at low temperature

We have observed cooldown-to-cooldown changes in the reverse-bias dark current of some very long-wavelength (cutoff >14 μm) HgCdTe P-on-n heterojunction photodiodes operated at very low temperatures (40–45 K). Other photodiodes in the same arrays are stable between cooldowns. The unstable ones have high dark currents, in the tail of the dark current distribution. Current-voltage analysis indicates that the high dark current is caused by trap-assisted tunneling and that the number of traps changes from cooldown to cooldown. Devices with negligible trap-assisted tunneling current, limited by diffusion and band-to-band tunneling currents at reverse bias, are stable between cooldowns. Both types of devices are stable within a given cooldown over periods of at least 24 h.     

硅基HgCdTe光伏器件的暗电流特性分析

对硅基HgCdTe中波器件进行了变温电流电压特性的测试和分析。测量温度从30K到240K，得到R0对数与温度的1000／T的实验曲线及拟合结果。同时选取60K、80K及110K下动态阻抗尺与电压V的曲线进行拟合分析。研究表明在我们器件工作的温度点80K，零偏压附近主要的电流机制是产生复合电流和陷阱辅助隧穿电流。要提高器件的水平，必须降低陷阱辅助隧穿电流和产生复合电流对暗电流的贡献。     

MMVCX光伏型HgCdTe中波探测器暗电流温度特性

研究了光伏型HgCdTe中波探测器的暗电流与烘烤时间的关系特性.编写了一种适用于n-on-p型的中波HgCdTe红外探测器的解析拟合程序.结合暗电流的主导机制有扩散机制、产生复合机制、带间直接隧穿机制和陷阱辅助隧穿机制.通过对样品不同烘烤时间的R-V曲线的解析拟合,得到了它们的暗电流成分,提取了6个特征参数.通过对比不同烘烤时间特征参数的变化,分析了烘烤对器件的影响.     

Numerical Analysis of Current–Voltage Characteristics of LWIR nBn and p-on-n HgCdTe Photodetectors

We performed numerical analysis of the current–voltage characteristics of long-wavelength infrared unipolar HgCdTe nBn photodetectors and compared those results with those of conventional p-on-n HgCdTe photodiodes. A computer program was applied to explain in detail the impact of the charge carrier generation and recombination processes on current densities. In our model the carrier diffusion, thermal generation–recombination, band-to-band tunneling, trap-assisted tunneling (via states located at mercury vacancies as well as dislocation cores), and impact ionization are included as potential limiting mechanisms. To validate the model, we compared the theoretical predictions with experimental data of high-quality p-on-n photodiodes published in the literature.     

光伏型碲镉汞长波探测器暗电流特性的参数提取研究

报道了一种适用于碲镉汞长波光伏探测器的由典型电阻电压(R-V)曲线提取器件基本特征参数的数据处理途径.拟合程序中采用的暗电流机制包括了扩散电流机制,产生复合电流机制,陷阱辅助隧穿机制以及带到带直接隧穿电流机制.本文详细地给出了该拟合计算所采用的方法和途径,分析了拟合参数的误差范围.通过对实际器件的R-V特性曲线的拟合计算,给出了实际器件的基本特征参数,验证了该数据处理途径的实用性.     

Current voltage modeling of current limiting mechanisms in HgCdTe focal plane array photodetectors

An automated iterative nonlinear fitting program has been developed to model current-voltage (I–V) data measured on HgCdTe infrared (IR) detector diodes. This model includes the ideal diode diffusion, generation-recombination, band-to-band tunneling, trap-assisted tunneling (TAT), and avalanche breakdown as potential current limiting mechanisms in an IR detector diode. The modeling presented herein allows one to easily distinguish, and more importantly to quantitatively compare, the amount of influence each current limiting mechanism has on various detectors’ I–V characteristics. Longer cutoff wavelength detectors often exhibit significant current limitations due to tunneling processes. The temperature dependence of these tunneling characteristics is thoroughly investigated for two diodes.     

不同厚度超薄栅氧化物MOSFET的应力诱导漏电流

研究了不同厚度的超薄栅1.9nm到3.0nm器件在恒压应力下的栅电流变化.实验结果显示应力诱导漏电流包括两个部分,一部分是由界面陷阱辅助隧穿引起的,另一部分是氧化物陷阱辅助隧穿引起的.     

不同厚度超薄栅氧化物MOSFET的应力诱导漏电流

研究了不同厚度的超薄栅1.9nm到3.0 nm器件在恒压应力下的栅电流变化.实验结果显示应力诱导漏电流包括两个部分,一部分是由界面陷阱辅助隧穿引起的,另一部分是氧化物陷阱辅助隧穿引起的.     

Mechanisms of interface trap-induced drain leakage current inoff-state n-MOSFET's

An interface trap-assisted tunneling and thermionic emission model has been developed to study an increased drain leakage current in off-state n-MOSFET's after hot carrier stress. In the model, a complete band-trap-band leakage path is formed at the Si/SiO₂ interface by hole emission from interface traps to a valence band and electron emission from interface traps to a conduction band. Both hole and electron emissions are carried out via quantum tunneling or thermal excitation. In this experiment, a 0.5 μm n-MOSFET was subjected to a dc voltage stress to generate interface traps. The drain leakage current was characterized to compare with the model. Our study reveals that the interface trap-assisted two-step tunneling, hole tunneling followed by electron tunneling, holds responsibility for the leakage current at a large drain-to-gate bias (V_dg). The lateral field plays a major role in the two-step tunneling process. The additional drain leakage current due to band-trap-band tunneling is adequately described by an analytical expression ΔI_d=Aexp(B_it/F). The value of B_it about 13 mV/cm was obtained in a stressed MOSFET, which is significantly lower than in the GIDL current attributed to direct band-to-band tunneling. As V_dg decreases, a thermionic-field emission mechanism, hole thermionic emission and electron tunneling, becomes a primary leakage path. At a sufficiently low V_dg, our model reduces to the Shockley-Read-Hall theory and thermal generation of electron-hole pairs through traps is dominant     

A new I-V model for stress-induced leakage current includinginelastic tunneling

A new I-V model to quantitatively represent stress-induced leakage current (SILC) is presented and compared with the experimental I-V characteristics. The trap-assisted tunneling model is modified so as to include the energy relaxation of tunneling electrons, which has been experimentally verified by applying the carrier separation technique to MOSFETs with the SILC component. The energy relaxation is treated in the new model as the change in the energy level of traps before and after the capture of electrons during two-step tunneling. It is demonstrated that this model successfully represents the experimental I-V characteristics of the SILC component and, particularly, the low apparent barrier height in the Fowler-Nordheim (FN) plot of the SILC component. The calculated low barrier height is attributed to the dominance of direct tunneling mechanism on both tunneling into traps and out of traps. The impact of the energy relaxation during tunneling, used in the present model, on the I-V characteristics is discussed in terms of the trap distribution inside the gate oxide, compared with conventional elastic tunneling model     

Analysis of dark current in IR detectors on thinned p-type HgCdTe

A model for the diffusion dark current in MIS IR detectors on thinned bulk p-type HgCdTe is discussed. The model includes trap-assisted tunneling mechanisms in the back-side depletion region as well as the effects of fast surface states. Expressions for the net recombination rate are developed for situations in which trap-assisted tunneling transitions are allowed. Calculations for 12-μm optical cutoff detectors operating at liquid-nitrogen temperature show that the properties of the back side, including surface fixed charge density, depletion region trap density, fast surface-state density, and majority carrier concentration, have a strong influence on the dark current levels of detectors on thin material. It is predicted that typical as-fabricated surface parameters will not result in large dark current densities. Calculations for detectors with surface parameters common to stressed (degraded) back surfaces, however, show dark current densities which would significantly affect detector performance     

Analysis of 1/f noise in LWIR HgCdTe photodiodes

We study the 1/f noise currents and dark currents in LWIR HgCdTe photodiodes. The measured dark currents of the diodes processed by post implantation annealing with different annealing times are analyzed using current model fitting methods. The different dark current components, such as diffusion current, generation-recombination current, band-to-band tunneling current, and trap assisted tunneling current, at various bias voltages can be separated from the measured dark currents. By the fitting analysis, some physical parameters are extracted and different annealing effects can be explained by the parameters. The improvements in diode characteristics by post implantation annealing can be explained by the changes of trap density, donor concentration, minority carrier lifetime, and generation lifetime. The 1/f noise currents are measured over a wide range of reverse bias voltages, and correlated with the extracted dark currents by superposition of the noise generated by the different dark current mechanisms. It turns out that the band-to-band tunneling has a smaller correlation with the 1/f noise than other current components, and the trap center seems to be responsible for the 1/f noise characteristics of the LWIR HgCdTe photodiodes.     

A new recombination model for device simulation including tunneling

A recombination model for device simulation that includes both trap-assisted tunneling (under forward and reverse bias) and band-to-band tunneling (Zener tunneling) is presented. The model is formulated in terms of analytical functions of local variables, which makes it easy to implement in a numerical device simulator. The trap-assisted tunneling effect is described by an expression that for weak electric fields reduces to the conventional Shockley-Read-Hall (SRH) expression for recombination via traps. Compared to the conventional SRH expression, the model has one extra physical parameter, the effective mass m*. For m*=0.25 m₀ the model correctly describes the experimental observations associated with tunneling. The band-to-band tunneling contribution is found to be important at room temperature for electric fields larger than 7×10⁵ V/cm. For dopant concentrations above 5×10¹⁷ cm^-3 or, equivalently, for breakdown voltages below approximately 5 V, the reverse characteristics are dominated by band-to-band tunneling     

Numerical Simulation of Bottom Oxide Thickness Effect on Charge Retention in SONOS Flash Memory Cells

In this paper, bottom-oxide thickness (T_bo) and program/erase stress effects on charge retention in SONOS Flash memory cells with FN programming are investigated. Utilizing a numerical analysis based on a multiple electron-trapping model to solve the Shockley-Read-Hall rate equations in nitride, we simulate the electron-retention behavior in a SONOS cell with T_bo from 1.8 to 5.0 nm. In our model, the nitride traps have a continuous energy distribution. A series of Frenkel-Poole (FP) excitation of trapped electrons to the conduction band and electron recapture into nitride traps feature the transitions between the conduction band and trap states. Conduction band electron tunneling via oxide traps created by high-voltage stress and trapped electron direct tunneling through the bottom oxide are included to describe various charge leakage paths. We measure the nitride-charge leakage current directly in a large-area device for comparison. This paper reveals that the charge-retention loss in a high-voltage stressed cell, with a thicker bottom oxide (5 nm), exhibits two stages. The charge-leakage current is limited by oxide trap-assisted tunneling in the first stage and, then, follows a 1/t time dependence due to the FP emission in the second stage. The transition time from the first stage to the second stage is related to oxide trap-assisted tunneling time but is prolonged by a factor     

Leakage mechanisms in the heavily doped gated diode structures

A leakage current model is presented which shows very good agreement with reported experimental results on gated diode structures with contemporary ULSI dimensions. The leakage current is modeled as the Shockley-Read-Hall generation current, enhanced by the Poole-Frenkel effect and trap-assisted tunneling. The model shows very good agreement on gate voltage, temperature, and oxide thickness dependence for the normal operating voltage range. It is found from the model that the doping range from 2×10¹⁸ to 1×10¹⁹ cm ^-3 gives the most significant degradation to the leakage characteristics in trench-type DRAM cells and the drain of MOSFETs     

The Physical Background of JUNCAP2

A new physics-based junction model for CMOS, called JUNCAP2, is presented. It contains new single-piece formulations for the Shockley–Read–Hall generation/recombination current and the trap-assisted tunneling (TAT) current, which are valid both in forward and reverse mode of operation. Moreover, the TAT model extends the existing model (IEEE Trans. Electron Devices, vol. 39, p. 2090, 1992) to the high electric fields encountered in today's CMOS technologies. Furthermore, the model contains expressions for junction capacitance, ideal current, band-to-band tunneling current, avalanche breakdown, and junction shot noise. The parameter extraction is also discussed in this paper.     

A model of the stress induced leakage current in gate oxides

A new quantitative model of the stress induced leakage current (SILC) in MOS capacitors with thin oxide layers has been developed by assuming the inelastic trap-assisted tunneling as the conduction mechanism. The oxide band structure has been simplified by replacing the trapezoidal barrier with two rectangular barriers. An excellent agreement between simulations and experiments has been found by adopting a trap distribution Gaussian in space and in energy. Only minor variations of the trap distribution parameters were observed by increasing the injected charge during electrical stress, indicating that oxide neutral defects with similar characteristics are generated at any stage of the stress     

一种氮化镓高迁移率晶体管的栅电流噪声模型

This work presents a theoretical and experimental study on the gate current 1/f noise in Al Ga N/Ga N HEMTs. Based on the carrier number fluctuation in the two-dimensional electron gas channel of Al Ga N/Ga N HEMTs, a gate current 1/f noise model containing a trap-assisted tunneling current and a space charge limited current is built. The simulation results are in good agreement with the experiment. Experiments show that, if Vg Vx, gate current 1/f noise comes from not only the trap-assisted tunneling RTS, but also the space charge limited current RTS. This indicates that the gate current 1/f noise of the Ga N-based HEMTs device is sensitive to the interaction of defects and the piezoelectric relaxation. It provides a useful characterization tool for deeper information about the defects and their evolution in Al Ga N/Ga N HEMTs.     

Modeling of Tunnelling Currents in Hf-Based Gate Stacks as a Function of Temperature and Extraction of Material Parameters

In this paper, we show that through electrical characterization and detailed quantum simulations of the capacitance-voltage and current-voltage (I-V) characteristics, it is possible to extract a series of material parameters of alternative gate dielectrics. We have focused on HfO₂ and HfSi_XO_YN_Z gate stacks and have extracted information on the nature of localized states in the dielectric responsible for a trap-assisted tunneling (TAT) current component and for the temperature behavior of the I-V characteristics. Simulations are based on a one-dimensional Poisson-Schroumldinger solver capable to provide the pure tunneling current and TAT component. Energy and capture cross section of traps responsible for TAT current have been extracted