Receiver Performances Considering Effects of Gain Control and Quantization in FDM-Based Narrowband Communication Systems

In wireless receivers, in order to prevent the saturation of a received signal in an analog-to-digital converter (ADC), an automatic gain control (AGC), which maintains the amplitude of an analog signal at an appropriate fixed level, is frequently employed. This paper discusses the effects of gain control and quantization in the AGC and ADC on the receiver performance in frequency division multiplexing-based narrowband communication systems. Each communication channel is very narrow in these systems, so the channels are packed without breaks, making it difficult to extract the desired signal using an analog bandpass filter. Therefore, other multiple communication signals are in-band interference signals in these systems. In comparison with a single interference signal, a peak amplitude of multiple interference signals is greater than the that of single interference signal given the same interference power. It is well known that signals having a large peak value cause the degradation of bit resolution due to the AGC and ADC processes. The purpose of this paper is to provide a theoretical and numerical analysis of the effects of gain control and quantization on the receiver performance in such an environment. The analysis results indicated that (i) in-band interference signals decreased the bit resolution of the desired signal amplitude because of these processes and (ii) the effects of these processes depend on the amplitude intensity and the number of in-band interference signals, given the same interference power.     

基于FPGA的中频AGC电路设计

传统数字自动增益控制（AGC）电路采用模数转换器（ADC）采集信号后进行信号处理得到幅值信息实现自动增益控制,此过程对采样速率和算法要求较高。为降低对ADC采样速率和后级信号处理算法要求,设计了一种采用高速比较器与数字器件（DAC＋FPGA/CPLD）实现的峰值检测电路,并将其应用在中频数字自动增益控制电路中,电路可以在1 MHz至60 MHz对信号进行自动增益控制,可以将峰峰值稳定在2±0.2 V范围。     

Foreground calibration technique of a pipeline ADC using capacitor ratio of Multiplying Digital-to-Analog Converter (MDAC)

A foreground calibration technique of a pipeline analog-to-digital converter (ADC) has been presented in this paper. This work puts an emphasis on erroneous ADC output occurring due to device mismatch, which, in any standard CMOS process boils down to capacitor mismatch. Deviation of gain of a multiplying digital-to-analog converter (MDAC), also known as the radix of a pipeline ADC stage, from its ideal values adds to the non-linearity of the ADC output. Capacitor mismatch is a major contributor for such an error. The proposed foreground calibration technique makes use of a simple arithmetic unit to extract the radix value from the ADC output for calibration. It uses a sinusoidal signal at the input for calibration purposes. The input sinusoidal signal can be sampled by the ADC clock at any rate for the calibration algorithm to be successful. Behavioral simulation of a pipeline ADC with 5% capacitor mismatch supports the established technique. To verify the calibration algorithm further, pipeline ADCs of different resolutions have been designed and simulated in a 0.18 μm CMOS process.     

SFD-AGC algorithm with ADC digitalizing bit fully utilized and stable PAR

Aiming at making full use of analog to digital converter (ADC) digitalizing bit without oversaturation while keeping peak to average ratio (PAR) stable, this paper puts forward a new segmented full-digital (SFD)-automatic gain control (AGC) algorithm for a new long term evolution (LTE) communication system. Segmented digital gain control strategy is adopted to adjust the gain by only one step based on detected power status. Whether the gain needs to be adjusted is determined by current signal state derived from the change ranges of adjacent root mean square (RMS) of input signal, but not the difference between the power level of current signal and target signal. Software simulation and hardware implementing had been conducted with LTE frequency division dual (FDD) uplink signal and the results indicated that the proposed AGC algorithm can judge power status accurately and hence adjust the gain precisely in one step with a short delay, further, it can make full use of ADC digitalizing bit without oversaturation as well as keeping stable PAR. In addition, the mean error vector magnitude (EVM) was confined less than 1.6% to meet the 3rd generation partnership project (3GPP) standard well.     

一种低复杂度超宽带通信系统

超宽带通信系统首先要解决的问题是降低系统的功耗和硬件的复杂度。在研究基于TR技术的超宽带通信系统的基础上,提出一种降低ADC实现复杂性的方法,同时对ADC和AGC联合设计,降低超宽带通信系统实现的复杂性。仿真的结果表明,提出的ADC实现方法和传统的2 b ADC的性能相当,但复杂度降低;在前导序列时间内AGC能完成信号的合理放大,使之满足信号的接收解调需要,而在信息数据解调期间不用调整AGC的增益。     

A tri-mode Compass/GPS/Galileo RF receiver with all-digital automatic gain control loop

A tri-mode RF receiver with all digital automatic gain control (AGC) loop and non-uniform 2-bit analog-to-digital converter (ADC) is designed for the bands of GPS-L1, Galileo-E1 and Compass B1 in 0.18 μm CMOS process. The RF front-end, analog baseband and frequency synthesizer with voltage controlled oscillator (VCO) have been integrated, and there are only few off-chip components including bypass capacitances, matching network and TCXO. For anti-jamming consideration, an all digital AGC loop with relevant variable gain amplifier (VGA) and non-uniform ADC is implemented to suppress interference and avoid saturation of signal chain. While drawing 35 mA current, this receiver achieves a total noise figure of 4 dB and a maximum gain of 105 dB, with a die area of 2.4 × 2.4 mm².     

基于Simulink的数字AGC系统设计与仿真

在Simulink环境下搭建了数字自动增益控制（AGC）系统的仿真平台,该平台由中频信号模型、可控增益放大器、A/D采样与I、Q分离模型及峰值提取和AGC控制算法部分组成,各个部件与真实器件、模块相对应,且参数可变。该平台按照真实AGC系统的信号流程进行仿真,能够为数字AGC算法的性能进行预测和评估,为AGC系统的参数选择提供了分析工具。     

The application of automatic gain control to microwave radiometers

An automatic gain control system for stabilizing the gain of microwave radiometers is described. System analysis sets forth the requirements for gain and bandwidth of the AGC loop. Two systems are described. One is a continuous AGC system that maintains a constant detector voltage and, as a result, the system gain is a function of the input signal. For input signals which are small compared to the system noise temperatures the nonlinearity due to the AGC system is negligible. In the second system, the output of the detector is sampled when the receiver comparison switch is connected to the reference termination. Therefore, the gain of the system is not affected by the signal and no nonlinearity is caused by the AGC system. The effect of noise in the AGC loop is analyzed and it is shown that the time constant of the AGC system can be made shorter than the final system output filter without increasing the over-all system noise.     

基于解扩信号信噪比的处理增益分析

A/D转换过程带来的量化和饱和噪声降低了处理增益,也降低了解扩后再生信号的信噪比。推导出一个获得解扩信号信噪比的解析表达式,用于估计宽带码分多址（WCDMA）系统解扩过程带来的处理增益损失,并与一般基于AD转化器（ADC）输出信噪比的估计进行了比较。通过数值分析,该公式很容易估计出自动增益控制的最佳参考值,该参考值的变化只是略微影响到解扩输出信号的信噪比。同时发现传统分析所给出的参考值是次最优的,仿真结果证实了其正确性。     

A fast configurable AGC for front-end of digital hearing aids

This paper presents a fast configurable automatic gain control (AGC) with strong focus on fast acting control and low power consumption. This AGC includes two paths, main amplification path and gain adjusting path. Using the gain adjusting path through an extra amplifier provides a way for tracking and comparing the input signal with four adjusted thresholds to be judged for selecting the appropriate gain value for main amplification path. This mechanism of gain control is done by reorganization of input level and changing the resistance of feedback in main amplification path to generate smooth variation gain, without any interruption or delay in signal flow through the variable gain amplifier. Moreover, in order to protect the user from intense transients in variations of the input signal level, output level of variable gain amplifier is directly monitored using optimum threshold to reduce the overall gain using feedback control mechanism. The minimum power is consumed by gain adjusting path has almost no considerable on power consumption, it greatly improves hearing quality. Meanwhile, using a large size PMOS differential pair at the input improved the noise performance. Proposed AGC designed and simulated in TSMC 130-nm CMOS process. The post layout simulation results the maximal SNR is 84.6 dB in 100 Hz–19.6 kHz band-width and the total consumption power of this AGC is 78 μW at 1 V supply voltage. In addition, its gain is varied smoothly between 20 to 57 dB. Achieved results demonstrate that designed AGC meet the requirement of analog front end of hearing aids.

     

Digital background calibration for memory effects in pipelined analog-to-digital converters

Memory errors can occur in the stages of a pipelined analog-to-digital converter (ADC) due to several effects. These include capacitor dielectric absorption/relaxation, incomplete stage reset at high clock rates, and parasitic capacitance effects when opamps are shared between subsequent pipeline stages. This paper describes these sources of memory errors and the effect they have on overall ADC linearity. It is shown how these errors relate to and differ from interstage gain errors. Two new calibration algorithms are proposed that correct for memory errors by digital post-processing of the ADC output. Both algorithms operate in the background and so do not require conversion to be interrupted in order to track changes due to temperature and supply variations. The two algorithms are compared in terms of their system costs and their dependence on input signal statistics.     

A fully integrated feedback AGC loop for ZigBee (IEEE 802.15.4) RF transceiver applications

This work presents an efficient solution for automatic gain control (AGC) loop in ZigBee transceiver compatible to IEEE 802.15.4 standard. The design is based on a RF (Radio Frequency) and linear IF (Intermediate Frequency) chain where the signal amplification is done in the RF front-end blocks and analog VGAs (variable gain amplifiers). The gains of the RF block and VGA are digitally controlled by the DAGC (Digital AGC) block to ensure that the ADC (Analog-to-Digital Converter) operates inside its dynamic range. Feedback loop architecture is employed for the advantage of high linearity due to its inherent characteristic. The whole AGC loop has been integrated in the ZigBee transceiver which was fabricated in a 0.18 μm CMOS technology. The AGC loop achieves a dynamic range of about 95 dB with the gain error of less than ±0.5 dB. The two-channel VGAs and peak detectors occupy an area of 1.5 mm×0.4 mm and dissipate 1.71 mW from a single 1.8 V power supply. The DAGC has been integrated in the digital baseband processor and occupies an area of about 0.4 mm×0.4 mm. The max gain lock time of the AGC loop is about 1.25 μs.     

一种基于映射结构的新颖A/D转换器的研究和仿真

本文研究了一种新型的混沌A/D转换器,这是一种基于非线性映射结构的非流水式ADC,并提出基于开关电容的ADC电路设计.理论分析和实验仿真表明本文所提出的A/D转换器克服了流水结构A/D变换器多级之间的增益匹配和每级中A/D和D/A变换之间的匹配等主要影响精度的设计问题,具有对噪声干扰不敏感等特性,降低了对部分元器件的精度等要求,可能为高速高精度A/D转换器的设计提供一种新的途经.     

Quantized UWB Transmitted Reference Systems

Digital implementation of ultra-wideband receivers requires analog-to-digital conversion (ADC) at an extremely high speed, thereby limiting the available bit resolution. Herein, the effect of low bit resolution quantization on the performance of UWB transmitted reference receivers is investigated. It is verified that the gain of the automatic-gain-control (AGC) has a significant effect on the achievable performance. Because of the considerable performance loss of conventional transmitted reference receivers in the presence of a low resolution ADC a new family of receiver structures optimized and tailored to quantized observations is presented. In particular, the generalized- likelihood ratio test (GLRT) based on the quantized samples is derived and shown to provide modest performance gains relative to the infinite resolution GLRT rule employed on the quantized received signal suggesting that conventional receiver structures can also be employed in the presence of a low resolution ADC. Results reveal that four bits of resolution in combination with an optimal choice for the AGC gain are sufficient to closely approach the performance of an infinite resolution receiver.     

一种0.18μm数字工艺的12bit 100MS/s流水线型ADC设计

描述一个基于TSMC 0.18μm数字工艺的12 bit 100 Ms/s流水线模数转换器的设计实例。该模数转换器采用1.5bit每级结构,电源电压为1.8V。包括十级1.5 bit/stage和最后一级2bit Flash模数转换器,共产生22bit数字码,数字码经过数字校正电路产生12 bit的输出。该模数转换器省去了采样保持电路,电路模块包括:各个子流水级、共模电压生成模块、带隙基准电压生成模块、开关电容动态偏置模块、系统时钟生成模块、时间延迟对齐模块和数字校正电路模块。为了实现低功耗设计,在电路设计中综合采用了输入采样保持放大器消去、按比例缩小和动态偏置电路等技术。ADC实测结果,当以100 MHz的采样率对10MHz的正弦输入信号进行采样转换时,在其输出得到了73.23dB的SFDR,62.75dB的SNR,整体功耗仅为113mW。     

大动态范围AGC电路在接收机中的应用

自动增益控制电路(AGC)是接收机的重要控制电路之一。具体分析了自动增益控制电路的工作原理以及AGC的分类方式。利用可变增益放大器AD8367和其他模拟电路以及外部检波方式,设计了思维简洁、电路控制速度快的峰值型AGC电路。详细解释了芯片版图、增益控制与电压关系以及基于AD8367的闭环AGC电路系统。实验结果表明,基于AD8367的两级AGC控制电路频率达到70 MHz,动态范围80 dB等预期指标,可以方便地调整所需要的输出电平值,确保接收机正常工作。     

3G系统中AGC的FPGA设计实现

详细介绍了数字AGC的基本原理,3G接收机需要采用AGC电路处理输入的无线信号,从而给无线环路中的可变增益放大器或数控衰减器提供外部控制信号,使得无线链路输出基本恒定且与输入信号电平无关的信号给基带部分处理,同时在很宽的范围内保持线性。RF输入电压经IF放大后,检波器检测出该电压的包络。该包络电压经AGC处理后,产生增益可变器件的控制电压,从而减小IF的输入和增益。     

Decision-Directed Automatic Gain Control for MAPSK Systems

An automatic gain control (AGC) loop is presented for use withM-ary amplitude- and phase-shift keying (MAPSK) systems. The gain control amplifier is regulated by an error signal formed by the difference between the estimated amplitude level and the received amplitude level. The AGC performance is thus independent of the short-term average received signal energy. AGC loop analysis and simulation is presented forM-ary amplitude-shift keying (MASK) and quadrature amplitude-shift keying (QASK). The AGC is shown to have a negligible degradation on the symbol probability of error for most practical cases. A generalized AGC for an arbitrary MAPSK system is also presented.     

Digitally-controlled automatic gain control circuits for CMOS CCDcamera interface

Automatic gain control circuit (AGC) design techniques for CMOS CCD camera interface systems are described. The required gain of the proposed AGC is controlled directly by digital bits. The amplifying function of the AGC is divided into three stages for high-speed operation. A capacitor-segment combination technique considerably improves the effective bandwidth of the AGC. While the three-stage prototype shows 32 dB AGC dynamic range in 1/8 dB steps, the proposed two-stage AGC reduces the power and chip area further     

自动增益控制环路方程的一种简化处理方法及环路稳定时间分析

基于一种典型的自动增益控制(AGC)环路的模型，采用对数表示方式，简化了AGC环路的静态微动方程和动态运动方程。用数学模型动态表示出AGC环路输出信号和增益控制信号的变化过程，定量定性分析了AGC环路的稳定时间。仿真结果及实际应用验证了本文方法的有效性。