一种新的FIR滤波器脉动实现结构

为了提高FIR滤波器的处理速度,一个主要手段是并行处理技术.并行处理除了可以提高运算速度外,还可以提高FIR滤波器的数据通过率以及降低系统功耗.本文首先从多项式分解角度给出一种FIR滤波器的并行结构.通过对此并行FIR滤波器的分析,提出了一种新的FIR滤波器的脉动实现结构.这种结构与一般的实现FIR滤波器的脉动结构相比具有规模小、能适应更高处理速度的优点.     

多相并行FIR滤波器的FPGA高速实现方法

L路多相并行FIR滤波器的工作速率是单路串行FIR滤波器的L倍,基于多项式分解的多相并行FIR滤波器实现结构简单、计算复杂度小、滤波运算延迟少;针对多相并行FIR滤波器,给出了基于多项式分解的多相并行FIR滤波器优化实现结构的FPGA高速实现方法。归纳、整理和推导了2路至8路基于多项式分解的多相并行滤波器优化实现结构,并针对FPGA实现的具体特点给出了多相并行滤波器优化实现结构的FPGA高速实现方法。通过测试分析可知,给出的基于多项式分解的多相并行FIR滤波器优化实现结构的FPGA高速实现方法能够在FPGA上高速实现多相并行FIR滤波器。     

Q-shift复小波的一种新型构造方法及其在图像去噪中的应用

为了提高复小波变换的效率,本文提出了一种设计Q-shift复小波滤波器的新方法。与目前采用多相位矩阵的晶格分解结构得到正交小波的方法不同的是,这里从更为一般的完全重构滤波器组出发寻求满足特定要求的正交小波。不但可以构造出系数更为简单、运算更加方便的小波,而且可以实现任意精度的复小波变换。该方法的可拓展性好,可以很方便的添加如高阶消失矩等限制并简化设计过程。以普遍采用的Q-shift10/10小波为例,利用本文构造的正交小波可将复小波变换中的乘法运算降低到原来的1/3,而加法基本相当,且小波的频率选择性质更好。将其用于图像去噪的实验表明,采用本文构造的小波可以显著提高处理速度并得到更高的峰值信噪比(PSNR)。     

用于太赫兹高速通信的FIR滤波器64并行实现算法

为满足太赫兹无线通信系统对大容量基带信号处理算法的要求,基于直接从多项式分解导出的传统滤波器并行实现算法,通过矩阵变化推导出复杂度更小的快速有限冲激响应(FIR)滤波器并行实现。在此基础上通过张量积的表示给出了2并行、4并行和8并行的转换公式以及实现架构。既而推导出2N并行快速FIR滤波器的通用实现公式,并对比了优化前后的复杂度差异。最后给出了64并行的快速FIR滤波器的推导公式和具体实现架构,以及优化前后的硬件复杂度对比,64并行的快速FIR滤波器算法资源消耗更少。     

一类最佳数据压缩FIR滤波器与Daubechies 小波

提出了一种设计数据压缩FIR滤波器的新方法．该方法在不引入信息失真的前提下以最有效分解原信号为目的设计滤波器．由此设计的滤波器可以实现数据基于压缩目的的最优分解,能够最大可能地提取信号中的有用信息同时去除冗余信息．该分解过程与具有一定正则性的Daubechies小波的离散小波变换十分相似,该滤波器也和Daubechies小波分解滤波器完全相同,其原因是Daubechies在构造小波时引入的余项应为零．     

基于双正交小波的光阑小波滤波器

提出了一种应用于4f光学系统的光学小波滤波器的设计与制作方法.结合光学信号的优势与小波变换的优点,利用双正交小波的共轭镜像特性构造出了频域形式的分解和重构滤波器.通过将滤波器放置在4f系统的频谱面上对图像成功实现了二维分解和重构.另外还根据信息处理要求和采样器件的特性,制作了振幅型和位相型两种小波滤波器.这两套滤波器都...     

纯二维小波滤波器组及其在图像压缩中的应用

构造了一组新的纯二维不可分离的小波滤波器——全相位离散反余弦列率滤波器（APDICSF）。该滤波器具有五株排列的交错采样形式和良好的内插性能,适用于图像分解压缩。将其用于提升格式的预测和更新滤波器,得到与可分离小波滤波器组不同的图像分解方式,并用SPIHT实现图像的压缩编码。实验证明,APDICSF组的压缩效果好于经典的Neville滤波器,在图像压缩方面有良好的应用前景。     

17/11双正交小波的优化设计及其对图像压缩性能的分析

许多适合于图像编码的小波,如CDF-9/7,Winger-17/11(W-17/11),Villasenor-6/10和10/18(V-6/10和V-10/18)小波,其滤波器系数是无理数,需要用无限的计算精度实现对应的离散小波变换(DWT)。该文给出了一种参数化构造17/11双正交小波组的简便方法:首先把小波合成滤波器表示为用两个自由参数表达的三角多项式,然后把双正交小波的精确重构条件归结为一个线性方程组,最后求解此方程组得到对应的小波分解滤波器,从而得到了17/11双正交小波滤波器的参数表达式。通过调整表达式中的自由参数,可以随意构造具有所需特征的17/11线性相位小波滤波器。作为构造实例,构造出一种新的有理系数17/11双正交小波滤波器,它具有优化的编码增益。实验表明:其压缩性能与W-17/11和V-10/18小波滤波器相当,优于CDF-9/7和V-6/10小波滤波器。     

一种人工神经网络自适应IIR滤波器

本文提出了一种人工神经网络自适应ＩＩＲ滤波器，这种自适应ＩＩＲ滤波器采用并联型结构，用人工神经网络实现，并保证系统在自适应过程中的稳定性，从而得到了一种稳定的、高度并行的自适应ＩＩＲ滤波器，从根本上改变了以往的串行数值迭代系统，使滤波器自适应过程仅需要几个微秒就可以完成。从而有可能用神经自适应系统完成对快速变化信号的实时处理。本文给出了计算机模拟的结果，理论和模拟结果均表明该结构是稳定的，收敛速度也有明显增加。     

双运算核提升小波变换的FPGA硬件实现

应用提升方法实现了双正交小波变换.给出了应用因式分解法,将传统小波滤波器分解为基本提升步骤的推导.采用双运算核在FPGA硬件平台上实现小波变换模块.采用单一时钟,在不增加系统设计复杂性和功耗的情况下,使得系统达到实时处理的要求.系统通过仿真验证,工作稳定可靠.     

基于多项式分解的自适应FIR滤波器脉动结构

该文由多项式信号的并行表达得到一种FIR滤波器并行结构。通过对FIR滤波器并行结构的分析,提出了几种自适应FIR滤波器的并行处理算法．同时给出了相应的脉动实现结构。     

Parallel pipeline implementation of wavelet transforms

Wavelet transforms have been one of the important signal processing developments in the last decade, especially for applications such as time-frequency analysis, data compression, segmentation and vision. Although several efficient implementations of wavelet transforms have been derived, their computational burden is still considerable. The paper describes two generic parallel implementations of wavelet transforms, based on the pipeline processor farming methodology, which have the potential to achieve real-time performance. Results show that the parallel implementation of the oversampled wavelet transform achieves virtually linear speedup, while the parallel implementation of the discrete wavelet transform (DWT) also outperforms the sequential version, provided that the filter order is large. The DWT parallelisation performance improves with increasing data length and filter order, while the frequency-domain implementation performance is independent of wavelet filter order. Parallel pipeline implementations are currently suitable for processing multidimensional images with data length at least 512 pixels     

一种新的高速自适应滤波的脉动实现结构

LMS算法具有计算简单,易于实现的特点,被广泛应用于诸如通信和雷达等许多信号处理领域,对其高速实现结构的研究一直是滤波器结构设计中的一个研究重点和热点。该文基于并行流水线LMS(PIPLMS)算法,设计了一种高速自适应滤波器脉动结构。该结构既具有脉动结构的高度流水特性,又具有一定的并行性。与已有结构相比,该文设计的结构具有更高的数据吞吐率。同时由于其并行特性,该结构还具有更低的系统功耗,更大的步长因子选择范围和更快的收敛速度。     

Block decomposition structures for the fast modular implementation of two-dimensional digital filters

A general structure is presented for the block realization of two-dimensional infinite impulse response digital filters, which is based on the two-dimensional matrix convolution equations and the decomposition of their associated transfer function matrices. The proposed decomposition may be considered as an extension of the scalar decomposition technique, which has already been used for the realization of two-dimensional digital filters associated with two-variable polynomials. The decomposition structure is considered in two different forms, which correspond to the direct forms I and II. It is shown that if a given two-dimensional single-input, single-output filter is realizable, then realizable block decomposition structures may be always selected. The proposed approach is general and applies without any restriction for the block implementation of any two-dimensional filter. The resulting structures are characterized by high inherent parallelism, modularity, regularity, reconfigurability, local interconnections, and very high sampling and throughput rates. Thus they are well suited for VLSI implementation and implementation via multiprocessor systems and array processors, such as systolic and wavefront arrays.     

Analog Implementation of Wavelet Transform in Switched-Current Circuits with High Approximation Precision and Minimum Circuit Coefficients

This paper presents a novel procedure for analog implementation of wavelet transform in switched-current (SI) circuits. An improved hybrid PSO–SQP optimization is employed to precisely approximate the impulse response of a filter to the wavelet base function in time domain. The SI first- and second-order section circuits with minimum coefficients are designed based on infinite-impulse-response digital filter technology. Cascode techniques are occupied to reduce the effects of parasitic elements. Based on these SI first- and second-order section circuits, a parallel wavelet circuit structure is presented to synthesize the approximated wavelet base function. By adjusting the switch clock frequency, the wavelets at different scales can be realized. The Gaussian wavelet is selected as an example to illustrate the design procedure. Simulation results demonstrate the feasibility of the proposed procedure for analog wavelet transform in SI circuits.     

Computation of DWT via FHT-based implementation

It is well known that most wavelet transform algorithms compute sampled coefficients of the continuous wavelet transform using the filter bank structure of the discrete wavelet transform (DWT). Although this method is efficient, noticeable computational savings have been obtained through an FFT-based implementation. The authors present a fast Hartley transform (FHT)-based implementation of the filter bank and show that noticeable overall computational savings can be obtained     

Low-power Analog VLSI Implementation of Wavelet Transform

For applications requiring low-power, low-voltage and real-time, a novel analog VLSI implementation of continuous Marr wavelet transform based on CMOS log-domain integrator is proposed.Mart wavelet is approximated by a parameterized class of function and with Levenbery-Marquardt nonlinear least square method,the optimum parameters of this function are obtained.The circuits of implementating Mart wavelet transform are composed of analog filter whose impulse response is the required wavelet.The filter design is based on IFLF structure with CMOS log-domain integrators as the main building blocks.SPICE simulations indicate an excellent approximations of ideal wavelet.