Dry etching fin process for SOI finFET manufacturing: Transition from 32 to 22 nm node on a 6T-SRAM cell

This work describes the main challenges encountered for patterning crystalline silicon (c-Si) fins when we scaled down the fin pitch from 124 to 90 nm on a 6T-SRAM cell. The target fins consist of straight structures (40 nm height and 17 nm of critical dimension) patterned on a 22 nm node with 90 nm fin pitch. The patterning stack consists of 70 nm of amorphous carbon as a hard mask with 25 nm of antireflective coating. Scaling down the fin pitch had a direct influence on the fin critical dimension, profile and sidewall roughness. We found out that the fin etching process developed for a 32 nm node with 124 nm fin pitch was no longer functional for patterning fins on a 22 nm node with 90 nm fin pitch, i.e., the critical dimension was wider than the target, the fins sidewalls were isotropically attacked and the profile was sloped. In order to reach 17 nm of critical dimension on 90 nm pitch we had to implement a new hard mask opening step. The c-Si fin sidewall roughness and fin profile were tuned by improving the uniformity across the wafers, optimizing the softlanding etch time and introducing a new overetch step with notch capability.     

Dry etching process for bulk finFET manufacturing

This paper describes a method to manufacture bulk fins for finFET. The bulk fins consist of two parts: the straight top of 125 nm height which is used as a fin and a sloped bottom of 200 nm one that facilitates the trench filling. The method is based on a conventional shallow trench isolation (STI) process flow with an additional α-C hard mask of 90 nm (with antireflective SiOC coating of 35 nm) on top of the STI stack (70 nm nitride on top of 8 nm oxide). The nitride layer and the top straight part of the fin is patterned using CH₂F₂/SF₆/N₂ chemistry and α-C as a mask, while the bottom sloped part is patterned using Cl₂/O₂/N₂ chemistry and the nitride layer as a mask. After the etching, the STI process flow remains almost unchanged.     

Polarimetry of illumination for 193 nm immersion lithography

We have constructed a theory of polarimetry of illumination used in 193 nm lithography equipments, fabricated a polarimeter mask, and demonstrated it for a hyper-NA (numerical aperture) immersion lithography scanner. The polarimeter mask comprises newly developed thin polarizers and wide-view-angle quarter-wave (λ/4) plates. Although a light traveling through these polarization devices on the polarimeter mask reaches an image detector at the wafer level through a projection optics, Stokes parameters of the illumination light can be measured with no influence from polarization characteristics of the projection optics between the mask and the image detector.     

Mirror electron microscope for inspecting nanometer-sized defects in magnetic media

We developed a mirror electron microscope (MEM) for the highly sensitive inspection of defects on the magnetic storage disks of commercial hard disk drives (HDDs). Magnetic fields recorded on a magnetic disk do not affect the MEM images for inspection. We used artificial defects in a detection sensitivity evaluation to test the effectiveness of our MEM inspection tool and found that it was sensitive enough to detect defects that were 67 nm in diameter and 7 nm in height. The size of a MEM image for a defect was eight times larger than the physical size measured by an atomic force microscope. The obtained sensitivity is beyond the resolution power of the objective lens of the MEM itself. This is because MEM images the distortion of static electrical potentials spread over a larger area than the physical size of a defect itself and the image is obtained in out-of-focus condition of an objective lens. The image acquisition time was 50 ms, which corresponded to the inspection time of 4 h for the full surface inspection of a 2.5 in. magnetic disk. MEM is a promising technique for conducting a highly sensitive defect inspection and a high throughput inspection simultaneously as compared with an SEM-based inspection.     

Al contacts to nanoroughened p-GaN

Nanoroughening of a p-GaN surface using nanoscale Ni islands as an etch mask was utilized to investigate the feasibility for the flip-chip configuration light-emitting diodes (LEDs) using an Al-based reflector. Improved ohmic characteristics were found for the nanoroughened sample. A specific contact resistivity of 8.9×10⁻² Ω cm² and a reflectance of 82% at 460 nm were measured for the nanoroughened Al contact. The Schottky barrier heights were decreased from 0.81 eV (I-V) and 0.84 eV (Norde) for the Al contact to 0.70 eV (I-V) and 0.69 eV (Norde) for the nanoroughened Al contact. The barrier height reduction may be attributed to enhanced tunneling and the increased contact area due to the nanoroughening. This work suggests that the ohmic contact characteristics and the light extraction efficiency may be improved further with a well-defined nanopatterned p-GaN layer.     

Silated acidic copolymers for nanoimprint lithography on flexible plastic substrates

A new silated acidic polymer was developed as the resist for nanoimprint lithography on flexible substrates. This polymer was synthesized from methylmethacrylate, n-butylacrylate, methacrylic acid and 3-[tris(trimethylsiloxy)silyl]propyl methacrylate by free radical copolymerization with an azobisisobutyronitrile (AIBN) initiator at 90 °C. The resist has excellent reactive ion etching (RIE) resistability, a lower T_g (43 °C) compared to poly(methyl methacrylate) (PMMA) and good flowability. It is suitable to use on flexible plastic substrates. The resist can be easily removed by an aqueous base solution at the final stripping step, instead of using an organic solvent or RIE. A 100 nm/50 nm (line/space) feature pattern was obtained on a flexible polyethylene terephthalate (PET)/ITO substrate.     

The structural and electrical properties of the SrTa2O6/In0.53Ga0.47As/InP system

The structural and electrical properties of SrTa₂O₆(SrTaO)/n-In_0.53GaAs_0.47(InGaAs)/InP structures where the SrTaO was grown by atomic vapor deposition, were investigated. Transmission electron microscopy revealed a uniform, amorphous SrTaO film having an atomically flat interface with the InGaAs substrate with a SrTaO film thickness of 11.2 nm. The amorphous SrTaO films (11.2 nm) exhibit a dielectric constant of ∼20, and a breakdown field of >8 MV/cm. A capacitance equivalent thickness of ∼1 nm is obtained for a SrTaO thickness of 3.4 nm, demonstrating the scaling potential of the SrTaO/InGaAs MOS system. Thinner SrTaO films (3.4 nm) exhibited increased non-uniformity in thickness. From the capacitance-voltage response of the SrTaO (3.4 nm)/n-InGaAs/InP structure, prior to any post deposition annealing, a peak interface state density of ∼2.3 × 10¹³ cm⁻² eV⁻¹ is obtained located at ∼0.28 eV (±0.05 eV) above the valence band energy (E_v) and the integrated interface state density in range E_v + 0.2 to E_v + 0.7 eV is 6.8 × 10¹² cm⁻². The peak energy position (0.28 ± 0.05 eV) and the energy distribution of the interface states are similar to other high-k layers on InGaAs, such as Al₂O₃ and LaAlO₃, providing further evidence that the interface defects in the high-k/InGaAs system are intrinsic defects related to the InGaAs surface.     

A pixel-based regularization approach to inverse lithography

Inverse lithography attempts to synthesize the input mask which leads to the desired output wafer pattern by inverting the forward model from mask to wafer. In this article, we extend our earlier framework for image prewarping to solve the mask design problem for coherent, incoherent, and partially coherent imaging systems. We also discuss the synthesis of three variants of phase shift masks (PSM); namely, attenuated (or weak) PSM, 100% transmission PSM, and strong PSM with chrome. A new two-step optimization strategy is introduced to promote the generation and placement of assist bar features. The regularization framework is extended to guarantee that the estimated PSM have only two or three (allowable) transmission values, and the aerial-image penalty term is introduced to boost the aerial image contrast and keep the side-lobes under control. Our approach uses the pixel-based mask representation, a continuous function formulation, and gradient-based iterative optimization techniques to solve the inverse problem. The continuous function formulation allows analytic calculation of the gradient in O(MNlog (MN)) operations for an M × N pattern making it practically feasible. We also present some results for coherent and incoherent imaging systems with very low k₁ values to demonstrate the effectiveness of our approach.     

A robust spacer gate process for deca-nanometer high-frequency MOSFETs

This paper, presents a robust spacer technology for definition of deca-nanometer gate length MOSFETs. Conformal deposition, selective anisotropic dry-etching and selective removal of sacrificial layers enabled patterning of an oxide hard mask with deca-nanometer lines combined with structures defined with I-line lithography on a wafer. The spacer gate technology produces negligible topographies on the hard mask and no residual particles could be detected on the wafer. The line-width roughness of 40 nm poly-Si gate lines was 4 nm and the conductance of 200 μm long lines exhibited a standard deviation of 6% across a wafer. nMOSFETs with 45 nm gate length exhibited controlled short-channel effects and the average maximum transconductance in saturation was 449 μS/μm with a standard deviation of 3.7% across a wafer. The devices exhibited a cut-off frequency above 100 GHz at a drain current of 315 μA/μm. The physical and electrical results show that the employed spacer gate technology is robust and can define deca-nanometer nMOSFETs with high yield and good uniformity.     

A simple method for high yield fabrication of sharp silicon tips

A simple, high yield, method for the fabrication of sharp silicon tips is described. A triangular etch mask design is used to ensure that the tip forms with a single point. An anisotropic wet etch gives rise to a tip that continues to “self-sharpen” after the etch mask is released. The tip geometry comprises three converging {1 1 3} planes towards the apex with {3 1 3} planes forming at the base. The apex of each tip typically has a radius of curvature of <5 nm, which can be reduced to <2 nm by a subsequent oxide sharpening process. Tips of this kind have been successfully integrated into the fabrication of atomic force microscopy probes.