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1.
In this article a new charge pump circuit is presented, which is feasible for implementation with the standard twin-well CMOS process. The proposed charge pump employs PMOS-switching dual charge-transfer paths and a simple two-phase clock. Since charge transfer switches are fully turned ON during each half of the clock cycle, they transfer charges completely from the present stage to the next stage without suffering threshold voltage drop. During one clock cycle, the pump transfers charges twice through two pumping paths which are operating alternately. Test chips have been fabricated in a 0.35-μm twin-well CMOS process. The output voltage of a 4-stage charge pump with each pumping capacitor of 7.36 pF measures 6.7 V under a 1.5 V power supply and 20 MHz clock frequency. It can supply a maximum load current of about 180 μA. Although the proposed circuit exhibits somewhat inferior performances against triple-well charge pumps using additional mask and process steps, it shows at least 60% higher voltage gain at V DD = 0.9 V, approximately 10% higher peak power efficiency at V DD = 1.5 V, much larger output current drivability and faster initial output rising than traditional twin-well charge pumps. This new pumping efficient circuit is suitable for design applications with a low-cost standard twin-well CMOS process.  相似文献   

2.
A new charge pump circuit with consideration of gate-oxide reliability is designed with two pumping branches in this paper. The charge transfer switches in the new proposed circuit can be completely turned on and turned off, so its pumping efficiency is higher than that of the traditional designs. Moreover, the maximum gate-source and gate-drain voltages of all devices in the proposed charge pump circuit do not exceed the normal operating power supply voltage (VDD). Two test chips have been implemented in a 0.35-/spl mu/m 3.3-V CMOS process to verify the new proposed charge pump circuit. The measured output voltage of the new proposed four-stage charge pump circuit with each pumping capacitor of 2 pF to drive the capacitive output load is around 8.8 V under 3.3-V power supply (VDD = 3.3 V), which is limited by the junction breakdown voltage of the parasitic pn-junction in the given process. The new proposed circuit is suitable for applications in low-voltage CMOS processes because of its high pumping efficiency and no overstress across the gate oxide of devices.  相似文献   

3.
This paper presents a novel organization of switch capacitor charge pump circuits based on voltage doubler structures. Each voltage doubler takes a DC input and outputs a doubled DC voltage. By cascading voltage doublers the output voltage increases up to 2 times. A two-phase voltage doubler and a multiphase voltage doubler structures are discussed and design considerations are presented. A simulator working in the Q-V realm was used for simplified circuit level simulation. In order to evaluate the power delivered by a charge pump, a resistive load is attached to the output of the charge pump and an equivalent capacitance is evaluated. To avoid the short circuit during switching, a clock pair generator is used to achieve multi-phase non-overlapping clock pairs. This paper also identifies optimum loading conditions for different configurations of the charge pumps. The proposed charge-pump circuit is designed and simulated by SPICE with TSMC 0.35-μm CMOS technology and operates with a 2.7 to 3.6 V supply voltage. It has an area of 0.4 mm2; it was designed with a frequency regulation of 1 MHz and internal current mode to reduce power consumption.  相似文献   

4.
为了提高驱动效率,设计了一种新颖的适用于BUCK型DC-DC的驱动电路,在芯片内部采用一个电荷泵和自适应死区时间控制逻辑的驱动电路。当芯片正常工作时,输出级低端LDNMOS管的驱动电平通过较大的电荷泵电容稳定在5.5V左右,输出级高端LDNMOS管的驱动电平通过自举电容高达29.93V,从而实现对DC-DC输出级高端和低端的驱动,这样既提高了驱动效率,又减少了对外部多个电源的需求。采用此电路的一款电流模BUCK型DC-DC已在UMC06μmBCD工艺线投片,芯片效率高达94%,输出级高端和低端LDNMOS的导通电阻为120mΩ,最大输出电流为5A,该驱动电路工作良好,芯片面积减小了15.4%。  相似文献   

5.
设计了一种基于传统Dickson结构的PMOS管传输型电荷泵电路。电路通过衬底电位跟随器实现PMOS管传输,避免了传输过程中阈值电压损失;通过电阻分压反馈网络、控制振荡器输出达到稳压的目的;在电荷泵不工作时,各个子电路关断,实现低功耗设计。仿真结果表明,电路效率高,上电时间短,纹波小;采用SMIC 0.18μm工艺流片,电路达到设计要求,输出高压稳定,驱动能力强,在1M EEPROM电路芯片中得到实际应用。  相似文献   

6.
提出一种新型浮栅MOS单管动态比较器的电路结构。以浮栅MOS单管为核心,根据浮栅电荷的保持特性,在时钟控制下,两个电压分时地输入浮栅MOS管从而引起浮栅电位变化,相对变化后的浮栅电位决定着比较管的再通断,使预充电的输出电容与源极电容重新分配电荷,通过输出电容上电压是否发生变化来反映比较结果。单管比较避免差分对管由于工艺偏差所引起的输入失调问题,而且以浮栅偏置抵消MOS管的阈值。采用charted0.35μmCMOS工艺设计电路,面积约为0.003mm2,经前、后仿真和流片测试,结果表明,电路功能正确。并且在3.3V电源电压下、比较时间为0.4μs时,平均功耗为2.8mW。  相似文献   

7.
A new high performance charge pump circuit is designed and realized in 0.18μm CMOS process. A wide input ranged rail-to-rail operational amplifier and self-biasing cascode current mirror are used to enable the charge pump current to be well matched in a wide output voltage range.Furthermore,a method of adding a precharging current source is proposed to increase the initial charge current,which will speed up the settling time of CPPLLs.Test results show that the current mismatching can be less than 0.4%in the output voltage range of 0.4 to 1.7 V,with a charge pump current of 100μA and a precharging current of 70μA.The average power consumption of the charge pump in the locked condition is around 0.9 mW under a 1.8 V supply voltage.  相似文献   

8.
提出了一种新颖的双模式高集成开关电容电荷泵。该电荷泵集成高频振荡器、电平移位、逻辑驱动以及4个功率MOSFET开关。与传统电荷泵相比,该电路可以工作在单电源以及双电源两种模式。单电源模式下,输出电压为-VCC;双电源模式下,输出电压为-3×VCC。电路采用0.35μm BCD工艺实现。测试结果表明:室温时,单电源模式和双电源模式下电荷泵输出电流分别为36 mA和80 mA时输出电压分别为-3.07 V和-12.10 V。在-55℃到125℃温度范围内,单电源模式和双电源模式下电荷泵输出电流分别为24 mA和50 mA时输出电压分别低于-3.06 V和-12.35 V。该电荷泵在两种模式下工作特性良好,已应用于相关工程项目。  相似文献   

9.
由于存在逆向电流,利用电流传输开关特性的改进型的电压泵(NCP-1)的电压增益被大大减弱.本论文提供了一个新的方法.通过使用双阈值电压CMOS代替单阈值电压CMOS,不但消除了逆向电流,而且对低电压有很好的放大增益.PSPICE模拟结果,当电源电压为0.5V时,6级电压泵可使输出电压放大到2.68V.  相似文献   

10.
A charge pump that utilizes a MOSFET body diode as a charge transfer switch is discussed. The body diode is characterized and a body diode model is developed for simulating the charge pump circuit. A 10% increase of voltage gain has been achieved in the proposed switching technique when compared with a traditional Dickson charge pump. The top plate and bottom plate switching technique have also been illustrated to improve the efficiency of the charge pump. A six-stage Dickson charge pump was designed to produce a 19 V output from a 3.3-V supply, using a 4 MHz, two-phase nonoverlapping clock signal driving the charge pump. The design was fabricated in a 0.35-/spl mu/m SOI CMOS process. An efficiency of 79% is achieved at a load current of approximately 19 /spl mu/A.  相似文献   

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