融合MEMS-IMU信息的亚像素相关跟踪方法

结合图像制导武器的工程应用,提出了一种融合微机电系统(Micro-Electro-Mechanical System, MEMS)-惯性测量单元(Inertial Measurement Unit,IMU)信息的亚像素相关跟踪方法。该方法采用基于速率测定的误差补偿方法对MEMS-IMU的测量误差进行补偿,以实现MEMS-IMU信息与图像数据的异质数据融合,同时采用基于模板插值的亚像素相关跟踪算法来提高跟踪精度。结果表明,该方法不仅可以较好地解决目前单靠图像信息提升图像跟踪精度时所面临的算法实时性与复杂度之间的冲突问题,而且还可以有效提升动基座下的图像跟踪精度。     

光电装备模拟训练数字跟踪转台实时仿真

针对光电对抗装备模拟训练中跟踪伺服转台实时性能仿真实现问题,运用数字转台概念,采用Matlab/RTW/xPC Target工具构建了能够模拟实物跟踪转台功能、性能的实时仿真分析环境,在普通PC机上实现了跟踪伺服转台实时性能的半实物仿真。完成了实时仿真分析平台软硬件及控制算法的设计与仿真测试,结果表明,该仿真方法能够模拟自动跟踪、外引导、操作手单杆跟踪三种状态下装备跟踪转台系统性能,既保证了实时性也大大减少了开发成本,也能够快捷高效进行跟踪控制算法的设计调试与快速控制原型实现,具有重要工程应用价值。     

一种实时视轴跟踪的IRST系统像移补偿控制技术

针对面阵凝视器件运用到红外搜索跟踪(IRST)系统中出现的图像拖尾问题,为解决方位搜索转台变速运动下高质量的IRST系统像移补偿,提出一种实时视轴跟踪的IRST系统像移补偿控制技术。基于方位搜索转台速率实时感知的振镜高速、高精度控制策略,实现了对像移的准确补偿。采用高精度M/T测速算法实现了像移的准确计算,通过对振镜电机建立控制系统模型,开展了振镜补偿控制算法仿真研究。实验室成像测试结果表明,在方位搜索转台任意变速运动下,靶标成像清晰无拖尾,成像效果与凝视型几无差别。     

基于FPGA的高速图像跟踪系统设计与实现

常规视觉跟踪系统用于导弹末制导等高速运动中时,图像目标会因出现变形、模糊等现象而影响跟踪精度。针对以上问题,设计实现了基于FPGA的高速图像跟踪系统。该系统通过125fps（frames per second）的高速图像采集目标信息,利用FPGA的并行运算特点,将形心计算嵌入到动态阈值法中来实现高速图像的实时目标检测,并根据形心相对于视场中央的偏移量控制云台跟踪高速运动目标,最后对投影上的目标进行了跟踪仿真实验。结果表明,系统可以实时跟踪高速运动目标,云台的跟踪速度约可达到50．7度/秒,改善了低速图像跟踪系统对高速运动目标跟踪误差大、精度低等问题。     

基于激光雷达的火箭主动漂移量测量技术

针对现有高速电视交会测量火箭漂移量受外界环境影响大和测量数据不能实时获取等问题,提出了基于激光雷达的火箭实时起飞漂移量主动测量方法。首先将激光雷达通过安装台安装在二维精密转台,在火箭发射过程中,二维精密转台带动激光雷达持续高精度跟踪扫描火箭的目标点位置,获取目标点位置对应的激光点云数据。接着,数据处理系统接收激光点云数据,拟合每一帧数据的椭圆曲线及其圆心位置,以火箭静止时椭圆圆心位置为基准位置,计算每一帧数据的椭圆圆心位置与基准位置的相对差值,确定火箭在起飞阶段的实时漂移量。最后,通过火箭发射试验验证文中提出的测量系统及测量方法,试验结果表明:在有环境干扰条件下,实时漂移量测量精度可达到3.1 cm,是目前火箭漂移量测量中精度最高的测量方法,同时可保证数据的实时性。为火箭发射的安控台提供了实时判别数据,保证了发射过程的安全。     

边界跟踪并行处理的新方法

针对边界跟踪的复杂问题,首次提出了边界跟踪问题的数据并行、处理并行的系统并行处理模式。在图像预处理中,实时实现了Ｒｏｂｅｒｔｓ算子和图像分割;在图像跟踪中,实时地实现了链码结构的边界跟踪;在硬件结构中,采用了功能流水线的方法,实现了图像采集、图像预处理,边界跟踪的综合集成,由此实现了边界的高速跟踪。论述了并行数据存取原理,介绍了边界跟踪系统的整体结构以及并行预处理,并行跟踪的方法,给出了边界跟踪的     

基于激光雷达与红外数据融合的跟踪算法

针对精确制导中目标的自动识别、稳定跟踪与抗干扰需求,提出了一种基于激光雷达与红外数据融合的目标识别与抗干扰方法。首先采用一致性点漂移(CPD)算法对目标在不同图像中的轮廓特性进行匹配,完成了激光与红外图像的配准;然后利用红外图像中目标的能量和形状信息、激光图像中的距离信息完成激光与红外图像的决策级融合;最后利用改进的核相关跟踪算法完成目标的跟踪与抗干扰。通过激光雷达与红外仿真数据的实验,验证了文中方法在目标跟踪与抗干扰性能上的有效性。     

基于传感器融合预测的改进跟踪前馈控制方法研究

针对光电跟踪系统中CCD相机反馈帧率较低，延迟较大导致跟踪高速目标能力差、响应能力差的问题，提出一种基于传感器融合预测的改进跟踪前馈控制方法。为减小融合获得目标高阶运动状态噪声大的问题，提出一种基于微分跟踪的传感器融合策略；针对图像反馈延迟问题，提出一种降阶匀加速Kalman模型，根据融合获得的运动学信息，结合Kalman滤波进行预测跟踪，补偿脱靶量的时间延迟，得到近似真实的目标位置和速度、加速度信息；针对低频输入信号引入闭环扰动问题，提出一种快速数据扩展方法，实现低频信号到高频信号的扩展；根据传感器融合预测结果，设计跟踪前馈控制器，提高系统的响应速度。仿真结果和实验结果均表明该前馈方法能够对CCD反馈延迟导致的跟踪误差进行补偿。实验结果表明：该方法能够大幅提高系统对高速目标的跟踪性能，在目标运动状态相同条件下，相比补偿前跟踪误差减小约83.67%。     

三片CCD构成的高速彩色电视摄像机

1 高速电视摄像机高速电视摄像机是将人眼看不到的非常高速的现象,通过慢动作使人能够看到详细过程的一种摄像机,摄像时,以600 frames/s的速度进行,回放时以30 frames/s的速度进行,这样可使肉眼看不到的现象变得可见。RGB—Rabbit高速摄像机可用600 frames/s的高速度进行摄影,以600 frames/s的速度摄取的图像用30 frames/s的速度回放时,将原速度放缓了约20倍,这就使其变得可见。进而还可以低于30 frames/s的速度回放,可以观看到更低速的图像。     

一种数字电视关联场景信息的传输方式及其系统

随着数字电视技术的持续发展和三网融合的不断推进,数字智能电视开始逐渐步入家庭。本文介绍一种高效数字电视关联场景信息的传输方法及其系统,用于解决在智能电视高速发展中存在的大量场景信息的实时有效传输问题。     

基才时间信息的快速检索方法探究

本文研究了利用时间信息实现快速检索视频文件的方法,视频文件的压缩编码标准采用的是H．264,该方法主要包括视频分析和视频检索两个部分的研究。在视频分析部分,对码流中的IDR帧（关键帧）进行抓取和获得其时间、位置、大小等信息。并将得到的时间等信息存入至数据库。该部分的重点是时间信息的获取,由于负责传输码流的RTP数据分组的时间戳记录了码流的时间信息,所以着重描述了获取并且记录RTP时间戳的过程。视频检索部分,利用时间等查询条件从数据库中进行视频检索。对所述方法进行研究。结果表明使用该方法能够快速查看某时刻视频内容．避免了检索视频时的重复处理。     

一种基于NS的网络视频QoS分析方法

为了建立网络中视频传输的QoS分析平台,在分析EvalVid工具集的基础上,选取NS-2作为仿真环境,提出一种网络视频的QoS分析方法。该方法首先从视频流中提取仿真用的trace文件,注入模拟的网络中传输,然后利用结果trace文件将原压缩视频文件中由于传输丢失和延时超过限制的分组丢弃,产生新的视频文件,解码后可进行质量的评价。通过实例证实提出的方案完全可行,并可以作为设计与研究视频传输问题的试验平台。     

ASIC implementation of a digital tachometer with high precision ina wide speed range

A common method in adjustable speed drives uses an incremental shaft encoder and an electronic circuit for velocity estimation. The usual method of counting pulses coming from the encoder in a fixed period of time produces a high-precision velocity estimate in the high-speed range. High precision in the low-speed range can be achieved measuring the elapsed time between two successive pulses coming from the encoder. In this paper, a mixed method that combines the best of the two previously mentioned approaches has been implemented using a simple electronic circuit based on one field-programmable gate array (FPGA) and one read-only memory (ROM)     

基于FPGA的视频信号采集技术研究

便携式裸眼3D设备的电路需要完成立体视频文件的解码播放和信号的实时处理,采用ARM+FPGA结构更有利于电路的研制。ARM系统支持Windows CE、安卓等操作系统,并具有LCD接口,通过FPGA采集ARM视频信号并暂存于随机存储器中,完成3D图像列插值、缩放后再输入3D液晶屏。探讨了使用FPGA器件完成数字视频信号的采集方法,得出数字视频采集的可行逻辑设计法,集成ARM与FPGA的综合优势来完成3D电路设计。系统性能经过初步验证,具有很好的可行性。     

A circuit-driven design methodology for video signal-processingdatapath elements

The programmable video signal processor (VSP) is an important category of processors for multimedia systems. Programmable video processors combine the flexibility of programmability with special architectural features that improve performance on video processing applications. VSPs are typically multiple processors with several processing elements (PEs) and a parallel memory system. This paper focuses on the architectural design of the PE's in a video processor and shows how technology and circuit parameters influence the structure of the datapath and, hence, the overall architecture of a programmable VSP. We emphasize the need to consider technological and circuit-level issues during the design of a system architecture and present a method whereby the conceptual organization of the PEs-the number of PEs, pipelining of the datapath, size of the register file, and number of register ports-can be evaluated in terms of a target set of applications before a detailed design is undertaken. We use motion-estimation and discrete cosine transform as example applications to illustrate how various technology parameters affect the architectural design choices. We show that the design of the register file and the datapath-pipeline depth can drastically affect PE utilization and, therefore, the number of PEs required for different applications. Our results demonstrate that pursuing the fastest cycle time can greatly increase the silicon area which must be devoted to PEs, due to both increased pipeline latency and reduced register file bandwidth     

A survey of future broadband multimedia satellite systems, issuesand trends

The demand for advanced information services is growing in terms of both the number of users and the services to be supported. Voice and low-rate data services are insufficient for users in a world where high-speed World Wide Web access is taken for granted. The trend is toward global information networks offering flexible multimedia information services to users on demand, anywhere, anytime. Potential services include video on demand, interactive video, fast Internet access, telemedicine, tele-education, and large file transfer. The need to support bandwidth-intensive multimedia services places new and challenging demands on satellite systems and networks. Flexibility, efficiency, mobility, and the ability to guarantee end-to-end quality of service are at a premium     

从64位Windows 7系统物理内存镜像中提取网络连接信息的方法

Memory analysis gains a weight in the area of computer live forensics.How to get network connection information is one of the challenges in memory analysis and plays an important role in identifying sources of malicious cyber attack. It is more difficult to find the drivers and get network connections information from a 64-bit windows 7 memory image file than from a 32-bit operating system memory image file. In this paper, an approach to find drivers and get network connection information from 64-bit windows 7 memory images is given. The method is verified on 64-bit windows 7 version 6.1.7600 and proved reliable and efficient.     

A 4-ns 4K×1-bit two-port BiCMOS SRAM

The authors introduce a two-port BiCMOS static random-access memory (SRAM) cell that combines ECL-level word-line voltage swings and emitter-follower bit-line coupling with a static CMOS latch for data storage. With this cell, referred to as a CMOS storage emitter access cell, it is possible to achieve access times comparable to those of high-speed bipolar SRAMs while preserving the high density and low power of CMOS memory arrays. The memory can be read and written simultaneously and is therefore well-suited to applications such as high-speed caches and video memories. A read access time of 3.8 ns at a power dissipation of 520 mW has been achieved in an experimental 4K×1-bit two-port memory integrated in a 1.5-μm 5-GHz BiCMOS technology. The access time in this prototype design is nearly temperature-insensitive, increasing to only 4 ns at a case temperature of 100°C     

A Novel Concept for High-Speed Time Switch Approaching Memory Read Cycle Limit

A novel concept and structure for a high-speed time division switch operating in the gigabit/second range are presented. The basic concept is to use the high-speed memory in the time switch effectively by means of a slow writing/fast reading method.Nnumbers of speech data are written in parallel duringNclock times and read serially during one clock time for one switched datum. By using the concept and high-speed memories that we have, a data switching system which approaches the memory and read cycle limit can be realized with a proper time margin.     

Design and analysis of high-speed random access memory with Coulombblockade charge confinement

A silicon-based memory cell utilizing Coulomb blockade is analyzed for use as a high-speed RAM. Operation principles and design guidelines are given by simple analytical modeling and simulations. By performing transient waveform Monte Carlo simulations, high-speed write operation is demonstrated with a time shorter than 10 ns. The memory node voltage of less than 0.1 V is detected by a newly proposed split-gate cell structure with a minimum disturbance to/from nonselected cells, which indicates the compatibility of this structure with conventional field effect transistors