Novel Quantum Dot Gate FETs and Nonvolatile Memories Using Lattice-Matched II–VI Gate Insulators

This paper presents the successful use of ZnS/ZnMgS and other II–VI layers (lattice-matched or pseudomorphic) as high-k gate dielectrics in the fabrication of quantum dot (QD) gate Si field-effect transistors (FETs) and nonvolatile memory structures. Quantum dot gate FETs and nonvolatile memories have been fabricated in two basic configurations: (1) monodispersed cladded Ge nanocrystals (e.g., GeO _x -cladded-Ge quantum dots) site-specifically self-assembled over the lattice-matched ZnMgS gate insulator in the channel region, and (2) ZnTe-ZnMgTe quantum dots formed by self-organization, using metalorganic chemical vapor-phase deposition (MOCVD), on ZnS-ZnMgS gate insulator layers grown epitaxially on Si substrates. Self-assembled GeO _x -cladded Ge QD gate FETs, exhibiting three-state behavior, are also described. Preliminary results on InGaAs-on-InP FETs, using ZnMgSeTe/ZnSe gate insulator layers, are presented.     

Novel Multistate Quantum Dot Gate FETs Using SiO2 and Lattice-Matched ZnS-ZnMgS-ZnS as Gate Insulators

Multistate behavior has been achieved in quantum dot gate field-effect transistor (QDGFET) configurations using either SiO _x -cladded Si or GeO _x -cladded Ge quantum dots (QDs) with asymmetric dot sizes. An alternative method is to use both SiO _x -cladded Si and GeO _x -cladded Ge QDs in QDGFETs. In this paper, we present experimental verification of four-state behavior observed in a QDGFET with cladded Si and Ge dots site-specifically self-assembled in the gate region over a thin SiO₂ tunnel layer on a Si substrate. This paper also investigates the use of lattice-matched high-κ ZnS-ZnMgS-ZnS layers as a gate insulator in mixed-dot Si QDGFETs. Quantum-mechanical simulation of the transfer characteristic (I _D–V _G) shows four-state behavior with two intermediate states between the conventional ON and OFF states.     

Quantum Dot Gate Three-State and Nonvolatile Memory Field-Effect Transistors Using a ZnS/ZnMgS/ZnS Heteroepitaxial Stack as a Tunnel Insulator on Silicon-on-Insulator Substrates

This paper describes the use of II–VI lattice-matched gate insulators in quantum dot gate three-state and flash nonvolatile memory structures. Using silicon-on-insulator wafers we have fabricated GeO _x -cladded Ge quantum dot (QD) floating gate nonvolatile memory field-effect transistor devices using ZnS-Zn_0.95Mg_0.05S-ZnS tunneling layers. The II–VI heteroepitaxial stack is nearly lattice-matched and is grown using metalorganic chemical vapor deposition on a silicon channel. This stack reduces the interface state density, improving threshold voltage variation, particularly in sub-22-nm devices. Simulations using self-consistent solutions of the Poisson and Schrödinger equations show the transfer of charge to the QD layers in three-state as well as nonvolatile memory cells.     

Indium Gallium Arsenide Quantum Dot Gate Field-Effect Transistor Using II–VI Tunnel Insulators Showing Three-State Behavior

This paper presents an indium gallium arsenide (InGaAs) quantum dot gate field-effect transistor (QDG-FET) that exhibits an intermediate “i” state in addition to the conventional ON and OFF states. The QDG-FET utilized a II–VI gate insulator stack consisting of lattice-matched ZnSe/ZnS/ZnMgS/ZnS/ZnSe for its high-κ and wide-bandgap properties. Germanium oxide (GeO _x )-cladded germanium quantum dots were self-assembled over the gate insulator stack, and they allow for the three-state behavior of the device. Electrical characteristics of the fabricated device are also presented.     

Four-State Sub-12-nm FETs Employing Lattice-Matched II–VI Barrier Layers

Three-state behavior has been demonstrated in Si and InGaAs field-effect transistors (FETs) when two layers of cladded quantum dots (QDs), such as SiO _x -cladded Si or GeO _x -cladded Ge, are assembled on the thin tunnel gate insulator. This paper describes FET structures that have the potential to exhibit four states. These structures include: (1) quantum dot gate (QDG) FETs with dissimilar dot layers, (2) quantum dot channel (QDC) with and without QDG layers, (3) spatial wavefunction switched (SWS) FETs with multiple coupled quantum well channels, and (4) hybrid SWS–QDC structures having multiple drains/sources. Four-state FETs enable compact low-power novel multivalued logic and two-bit memory architectures. Furthermore, we show that the performance of these FETs can be enhanced by the incorporation of II–VI nearly lattice-matched layers in place of gate oxides and quantum well/dot barriers or claddings. Lattice-matched high-energy gap layers cause reduction in interface state density and control of threshold voltage variability, while providing a higher dielectric constant than SiO₂. Simulations involving self-consistent solutions of the Poisson and Schrödinger equations, and transfer probability rate from channel (well or dot layer) to gate (QD layer) are used to design sub-12-nm FETs, which will aid the design of multibit logic and memory cells.     

Nonvolatile Memories Using Quantum Dot (QD) Floating Gates Assembled on II–VI Tunnel Insulators

This paper presents preliminary data on quantum dot gate nonvolatile memories using nearly lattice-matched ZnS/Zn_0.95Mg_0.05S/ZnS tunnel insulators. The GeO _x -cladded Ge and SiO _x -cladded Si quantum dots (QDs) are self-assembled site-specifically on the II–VI insulator grown epitaxially over the Si channel (formed between the source and drain region). The pseudomorphic II–VI stack serves both as a tunnel insulator and a high-κ dielectric. The effect of Mg incorporation in ZnMgS is also investigated. For the control gate insulator, we have used Si₃N₄ and SiO₂ layers grown by plasma- enhanced chemical vapor deposition.     

Nonvolatile Silicon Memory Using GeO<Subscript><Emphasis Type="Italic">x</Emphasis></Subscript>-Cladded Ge Quantum Dots Self-Assembled on SiO<Subscript>2</Subscript> and Lattice-Matched II–VI Tunnel Insulator

This paper presents fabrication and characterization of a quantum dot-based floating gate nonvolatile memory device with site-specific self-assembly of germanium oxide-cladded germanium (GeO _x -Ge) quantum dots on SiO₂ and ZnS/ZnMgS/ZnS (II–VI lattice-matched high-κ dielectric) tunnel insulator material. These monodispersed and individually cladded quantum dots have the potential to store charge uniformly in the floating gate and are well suited for nonvolatile memory applications.     

Nonvolatile Memory Effect in Indium Gallium Arsenide-Based Metal–Oxide–Semiconductor Devices Using II–VI Tunnel Insulators

This paper reports the successful use of ZnSe/ZnS/ZnMgS/ZnS/ZnSe as a gate insulator stack for an InGaAs-based metal–oxide–semiconductor (MOS) device, and demonstrates the threshold voltage shift required in nonvolatile memory devices using a floating gate quantum dot layer. An InGaAs-based nonvolatile memory MOS device was fabricated using a high-κ II–VI tunnel insulator stack and self-assembled GeO _x -cladded Ge quantum dots as the charge storage units. A Si₃N₄ layer was used as the control gate insulator. Capacitance–voltage data showed that, after applying a positive voltage to the gate of a MOS device, charges were being stored in the quantum dots. This was shown by the shift in the flat-band/threshold voltage, simulating the write process of a nonvolatile memory device.     

Core–Shell ZnxCd1?xSe/ZnyCd1?ySe Quantum Dots for Nonvolatile Memory and Electroluminescent Device Applications

This paper presents a floating quantum dot (QD) gate nonvolatile memory device using high-energy-gap Zn _y Cd_1−y Se-cladded Zn _x Cd_1−x Se quantum dots (y > x) with tunneling layers comprising nearly lattice-matched semiconductors (e.g., ZnS/ZnMgS) on Si channels. Also presented is the fabrication of an electroluminescent (EL) device with embedded cladded ZnCdSe quantum dots. These ZnCdSe quantum dots were embedded between indium tin oxide (ITO) on glass and a top Schottky metal electrode deposited on a thin CsF barrier. These QDs, which were nucleated in a photo-assisted microwave plasma (PMP) metalorganic chemical vapor deposition (MOCVD) reactor, were grown between the source and drain regions on a p-type silicon substrate of the nonvolatile memory device. The composition of QD cladding, which relates to the value of y in Zn _y Cd_1−y Se, was engineered by the intensity of ultraviolet light, which controlled the incorporation of zinc in ZnCdSe. The QD quality is comparable to those deposited by other methods. Characteristics and modeling of the II–VI quantum dots as well as two diverse types of devices are presented in this paper.     

Light-emitting tunneling nanostructures based on quantum dots in a Si and GaAs matrix

InGaAs/GaAs and Ge/Si light-emitting heterostructures with active regions consisting of a system of different-size nanoobjects, i.e., quantum dot layers, quantum wells, and a tunneling barrier are studied. The exchange of carriers preceding their radiative recombination is considered in the context of the tunneling interaction of nanoobjects. For the quantum well-InGaAs quantum dot layer system, an exciton tunneling mechanism is established. In such structures with a barrier thinner than 6 nm, anomalously fast carrier (exciton) transfer from the quantum well is observed. The role of the above-barrier resonance of states, which provides “instantaneous” injection into quantum dots, is considered. In Ge/Si structures, Ge quantum dots with heights comparable to the Ge/Si interface broadening are fabricated. The strong luminescence at a wavelength of 1.55 μm in such structures is explained not only by the high island-array density. The model is based on (i) an increase in the exciton oscillator strength due to the tunnel penetration of electrons into the quantum dot core at low temperatures (T < 60 K) and (ii) a redistribution of electronic states in the Δ₂-Δ₄ subbands as the temperature is increased to room temperature. Light-emitting diodes are fabricated based on both types of studied structures. Configuration versions of the active region are tested. It is shown that selective pumping of the injector and the tunnel transfer of “cold” carriers (excitons) are more efficient than their direct trapping by the nanoemitter.     

Electrical Characteristics of Triple‐Gate RSO Power MOSFET (TGRMOS) with Various Gate Configurations and Bias Conditions

In this paper, we propose a triple‐gate trench power MOSFET (TGRMOS) that is made through a modified RESURF stepped oxide (RSO) process, that is, the nitride_RSO process. The electrical characteristics of TGRMOSs, such as the blocking voltage (BV_DS) and on‐state current (I_D,MAX), are strongly dependent on the gate configuration and its bias condition. In the nitride_RSO process, the thick single insulation layer (SiO₂) of a conventional RSO power MOSFET is changed to a multilayered insulator (SiO₂/SiN_x/TEOS). The inserted SiN_x layer can create the selective etching of the TEOS layer between the gate oxide and poly‐Si layers. After additional oxidation and the poly‐Si filling processes, the gates are automatically separated into three parts. Moreover, to confirm the variation in the electrical properties of TGRMOSs, such as BV_DS and I_D,MAX, simulation studies are performed on the function of the gate configurations and their bias conditions. BV_DS and I_D,MAX are controlled from 87 V to 152 V and from 0.14 mA to 0.24 mA at a 15‐V gate voltage. This I_D,MAX variation indicates the specific on‐resistance modulation.     

The effects of quantum dot coverage in InAs/(In)GaAs nanostructures for long wavelength emission

We present a study on the effects of quantum dot coverage on the properties of InAs dots embedded in GaAs and in metamorphic In_0.15Ga_0.85As confining layers grown by molecular beam epitaxy on GaAs substrates. We show that redshifted emission wavelengths exceeding 1.3 μm at room temperature were obtained by the combined use of InGaAs confining layers and high quantum dot coverage. The use of high InAs coverage, however, leads to detrimental effects on the optical and electrical properties of the structures. We relate such behaviour to the formation of extended structural defects originating from relaxed large-sized quantum dots that nucleate in accordance to thermodynamic equilibrium theories predicting the quantum dot ripening. The effect of the reduced lattice-mismatch of InGaAs metamorphic layers on quantum dot ripening is discussed in comparison with the InAs/GaAs system.     

Spatial Wavefunction-Switched (SWS) InGaAs FETs with II–VI Gate Insulators

This paper presents the implementation of a novel InGaAs field-effect transistor (FET), using a ZnSe-ZnS-ZnMgS-ZnS stacked gate insulator, in a spatial wavefunction-switched (SWS) structural configuration. Unlike conventional FETs, SWS devices comprise two or more asymmetric coupled quantum wells (QWs). This feature enables carrier transfer vertically from one quantum well to another or laterally to the wells of adjacent SWS-FET devices by manipulation of the gate voltages (V _g). Observation of an extra peak (near both accumulation and inversion regions) in the capacitance–voltage data in an InGaAs-AlInAs two-quantum-well SWS structure is presented as evidence of spatial switching. The peaks are attributed to the appearance of carriers first in the lower well and subsequently their transfer to the upper well as the gate voltage is increased. The electrical characteristics of a fabricated SWS InGaAs FET are also presented along with simulations of capacitance–voltage (C–V) behavior, showing the effect of wavefunction switching between wells. Finally, logic operations involving simultaneous processing of multiple bits in a device, using coded spatial location of carriers in quantum well channels, are also described.     

A model of photoinduced annealing of intrinsic defects in hexagonal CdS<Subscript>x</Subscript>Se<Subscript>1−<Emphasis Type="Italic">x</Emphasis></Subscript> quantum dots

A possible mechanism of photoinduced annealing of intrinsic defects in quantum dots with a hexagonal crystal structure is justified on the basis of the studies of the kinetics of photoinduced decay of luminescence of CdS_xSe_1?x quantum dots synthesized in a glass matrix and ab initio calculations of chemical bond energies at the interface in the n(CdSe)-SiO_x-type cluster. The model proposed implies that photoinduced Se-O bond breaking at the anionic face results in an increase in electric field inside the quantum dot; this field stimulates cadmium vacancy diffusion to the surface. This model accounts for the degradation of luminescence and of the parameters of nonlinear optical devices observed during photoinduced annealing.     

Microstructural Aspects of Nucleation and Growth of (In,Ga)As-GaAs(001) Islands with Low Indium Content

Molecular beam epitaxy growth of multilayer In _x Ga_1-x As/GaAs(001) structures with low indium content (x = 0.20–0.35) was studied by X-ray diffraction and photoluminescence in order to understand the initial stage of strain-driven island formation. The structural properties of these superlattices were investigated using reciprocal space maps, which were obtained around the symmetric 004 and asymmetric 113 and 224 Bragg diffraction, and ω/2θ scans with a high-resolution diffractometer in the triple axis configuration. Using the information obtained from the reciprocal space maps, the 004 ω/2θ scans were simulated by dynamical diffraction theory and the in-plane strain in the dot lattice was determined. We determined the degree of vertical correlation for the dot position (“stacking”) and lateral composition modulation period (LCM) (lateral ordering of the dots). It is shown that initial stage formation of nanoislands is accompanied by LCM only for [110] direction in the plane with␣a period of about 50 to 60 nm, which is responsible for the formation of a quantum wire like structure. The role of In _x Ga_1-x As thickness and lateral composition modulation in the formation of quantum dots in strained In _x Ga_1-x As/GaAs structures is discussed.     

Optical properties of hybrid quantum-well–dots nanostructures grown by MOCVD

The deposition of In _x Ga_1–x As with an indium content of 0.3–0.5 and an average thickness of 3–27 single layers on a GaAs wafer by metalorganic chemical vapor deposition (MOCVD) at low temperatures results in the appearance of thickness and composition modulations in the layers being formed. Such structures can be considered to be intermediate nanostructures between ideal quantum wells and quantum dots. Depending on the average thickness and composition of the layers, the wavelength of the photoluminescence peak for the hybrid InGaAs quantum well–dots nanostructures varies from 950 to 1100 nm. The optimal average In _x Ga_1–x As thicknesses and compositions at which the emission wavelength is the longest with a high quantum efficiency retained are determined.     

Origin of the radiative emission in blue-green light emitting diodes based on GaN/InGaN heterostructures

Phase separation effects induced by spinodal decomposition taking place in cubic In_xGa_1−xN epitaxial layers were investigated by means of resonant Raman scattering (RRS) and X-ray diffractometry (XRD) experiments. The alloy epilayers were grown by radio-frequency plasma-assisted molecular beam epitaxy on GaAs (001) substrates. Ab initio theoretical calculation of the alloy phase diagram predicts the formation of In-rich phases in the layers which is confirmed by the RRS and XRD experiments. Photoluminescence observed at room temperature and 30 K from the layers shows light emission in the blue-green region of the spectrum. RRS experiments demonstrated that the observed emission is directly linked to the In-rich separated phases (quantum dots) in the alloy. The results support the model that the origin of light emission in nitride-based light emitting diodes and laser diodes is related to quantum confinement effects taking place in quantum dots formed in the InGaN layers, active media of the devices.     

Polarity Effects of Polymer Gate Electrets on Non‐Volatile Organic Field‐Effect Transistor Memory

Organic non‐volatile memory (ONVM) based on pentacene field‐effect transistors (FETs) has been fabricated using various chargeable thin polymer gate dielectrics—termed electrets—onto silicon oxide insulating layers. The overall transfer curve of organic FETs is significantly shifted in both positive and negative directions and the shifts in threshold voltage (V_Th) can be systemically and reversibly controlled via relatively brief application of the appropriate external gate bias. The shifted transfer curve is stable for a relatively long time—more than 10⁵ s. However, this significant reversible shift in V_Th is evident only in OFETs with non‐polar and hydrophobic polymer electret layers. Moreover, the magnitude of the memory window in this device is inversely proportional to the hydrophilicity (determined from the water contact angle) and dielectric polarity (determined from the dielectric constant), respectively. Memory behaviors of ONVM originate from charge storage in polymer gate electret layers. Therefore, the small shifts in V_Th in ONVM with hydrophilic and polar polymers may be due to very rapid dissipation of transferred charges through the conductive channels which form from dipoles, residual moisture, or ions in the polymer electret layers. It is verified that the surface or bulk conductivities of polymer gate electret layers played a critical role in determining the non‐volatile memory properties.     

Characterization of GaAs/ InxGa1−x As quantum-dot heterostructures by electrical and optical methods

Results of electrical and optical studies of GaAs/In_xGa_1−x As heterostructures are reported. The aim of these studies was to identify the quantum dots and develop a technology of their growth by spontaneous transformation of an In_xGa_1−x As layer. The surface charge at the depth of the quantum dots and their surface density as a function of the deposition time of this narrow-band material are estimated by C-V profiling. A photoluminescence study of the quantum dots revealed peculiarities of the filling of their electron states at various excitation levels. The influence of Coulomb interactions on the optical properties of the quantum dots is discussed. Fiz. Tekh. Poluprovodn. 32, 111–116 (January 1998)     

Hemoglobin‐CdTe‐CaCO3@Polyelectrolytes 3D Architecture: Fabrication,Characterization, and Application in Biosensing

A Hemoglobin‐CdTe‐CaCO₃@polyelectrolyte 3D architecture is synthesized by a stepwise layer‐by‐layer method and is further used to fabricate an electrochemistry biosensor. While the calcium carbonate (CaCO₃) microsphere acts as an effective host for the loading of cadmium telluride (CdTe) quantum dots due to its channel‐like structure, the polyelectrolyte layers further increase the loading amount and help in the formation of a thick and uniform quantum‐dot “shell”, which not only improves the stability of the spheres in water, but also contributes to the fast and effective direct electron transfer between the protein redox center and the macroscopic electrode. The materials are characterized and compared, and the possible mechanism for the direct electrochemistry phenomenon is hypothesized. Our work not only provides a facile and effective route for the preparation of quantum‐dot‐loaded spheres, but also sets an example of how the structure of functional materials can be tuned and related to their applications. In addition, it is one of the few examples of using CaCO₃ microspheres in quantum‐dot loading and biosensing.