一种新的低功耗BIST测试生成器设计

文章提出了一种在不损失固定型故障覆盖率的前提下降低测试功耗的BIST测试生成器设计方案,该方案在原始线性反馈移位寄存器的基础上添加简单的控制逻辑电路,对LFSR的输出和时钟进行调整,从而得到了准单输入跳变的测试向量集,使得待测电路的平均功耗大大降低.由于该设计方案比其它LPTPG方案的面积开销小,从而具有更好的使用价值.     

Deterministic built-in test pattern generation for high-performancecircuits using twisted-ring counters

We present a new approach for built-in test pattern generation based on the reseeding of twisted-ring counters (TRCs). The proposed technique embeds a precomputed deterministic test set for the circuit under test (CUT) in a short test sequence produced by a TRC. The TRC is designed using existing circuit flip-flops and does not add to hardware overhead beyond what is required for basic scan design. The test control logic is simple, uniform for all circuits, and can be shared among multiple CUTs. Furthermore, the proposed method requires no mapping logic between the test generator circuit and the CUT; hence it imposes no additional performance penalty. Experimental results for the ISCAS benchmark circuits show that it is indeed possible to embed the entire precomputed test set in a TRC sequence using only a small number of seeds     

An Efficient Deterministic Test Pattern Generator for Scan-Based BIST Environment

To obtain satisfactory fault coverage for testing a logic circuit, linear feedback shift registers (LFSRs) have been used to generate not only the pseudorandom, but also the deterministic patterns in the scan-based built-in self-test environment. However, like other scan-based methods, the LFSR based pattern generation schemes take a long test application time to feed deterministic patterns from the LFSR into a scan chain. In this paper we derive a general relationship between the bits in the scan chain and the states of the LFSR and show that any bit to be generated by an LFSR in any future clock cycle can be pre-generated by a linear function of the current LFSR state. With this relationship, we can divide a scan chain into multiple sub-chains and use one LFSR-based multiple sequence generator to simultaneously generate all the subsequences required by the sub-chains, hence can greatly reduce the test application time for deterministic patterns. Moreover, due to the scan time reduction, test power wasted during the scan operation can also be significantly reduced.     

An effective logic BIST scheme based on LFSR-reseeding and TVAC

An effective logic built-in self-test scheme aiming at reducing the area overhead of IC testing and improving the fault average is proposed, which combines strategies of linear feedback shift register (LFSR)-reseeding with test vectors applied by circuit-under-test itself (TVAC). LFSR-reseeding technology is first applied to decrease the size of test set and the number of interior feedback wires, while TVAC technology is applied to decrease the number of stored seeds. An efficient LFSR-reseeding algorithm and a modified quick judgment method for path search are proposed. Experimental results for ISCAS 85 benchmarks demonstrate that the proposed method reduces the number of interior feedback wires more than 50% on average and can achieve full fault coverage with much less groups as well as area overhead compared with previous TVACs.     

基于变周期重播种LFSR的测试生成

基于重播种的LFSR结构的伪随机测试生成中包含的冗余测试序列较多,因而其测试序列长度仍较长,耗费测试时间长,测试效率不高。针对此状况,提出基于变周期重播种的LFSR结构的测试生成方法。该方法可以有效地跳过伪随机测试生成中的大量冗余测试序列。在保证电路测试故障覆盖率不变的条件下,缩短总测试序列的长度。分析结果表明,同定长重播种方法相比,该方法能以较少的硬件开销实现测试序列的精简,加快了测试的速度,提高了电路测试诊断的效率。     

On methods to match a test pattern generator to acircuit-under-test

Autonomous circuits such as linear feedback shift registers (LFSRs) and cellular automats are used as low-cost test pattern generators for circuits testable by pseudo-random patterns. We demonstrate that different LFSRs of the same degree, started from different initial states, may yield significantly different fault coverages and test lengths when used as test pattern generators for a given circuit, especially when the circuit has faults which are hard to detect by a practical number of pseudo-random patterns. Methods to tailor an LFSR to a circuit-under-test are proposed, that attempt to select the most effective LFSR and initial state for the circuit. The first method is based on a learning process that can be applied directly to certain types of circuits. The learning process is also used to establish a collection of (primitive and nonprimitive) LFSRs and initial states, effective for arbitrary circuits. This collection can then be used as a starting point for a genetic optimization procedure aimed at improving the selected LFSR and initial state. The use of an LFSR that can apply complemented as well as uncomplemented test patterns is shown to significantly improve the fault coverage, at the cost of a small area overhead. Experimental results demonstrate the applicability of the proposed approaches to stuck-at faults and to transition faults     

A BIST TPG for Low Power Dissipation and High Fault Coverage

This paper presents a low hardware overhead test pattern generator (TPG) for scan-based built-in self-test (BIST) that can reduce switching activity in circuits under test (CUTs) during BIST and also achieve very high fault coverage with reasonable lengths of test sequences. The proposed BIST TPG decreases transitions that occur at scan inputs during scan shift operations and hence reduces switching activity in the CUT. The proposed BIST is comprised of two TPGs: LT-RTPG and 3-weight WRBIST. Test patterns generated by the LT-RTPG detect easy-to-detect faults and test patterns generated by the 3-weight WRBIST detect faults that remain undetected after LT-RTPG patterns are applied. The proposed BIST TPG does not require modification of mission logics, which can lead to performance degradation. Experimental results for ISCAS'89 benchmark circuits demonstrate that the proposed BIST can significantly reduce switching activity during BIST while achieving 100% fault coverage for all ISCAS'89 benchmark circuits. Larger reduction in switching activity is achieved in large circuits. Experimental results also show that the proposed BIST can be implemented with low area overhead.     

A New Built-in TPG Based on Berlekamp–Massey Algorithm

In this work, a new method to design a mixed-mode Test Pattern Generator (TPG) based only on a simple and single Linear Feedback Shift Register (LFSR) is described. Such an LFSR is synthesized by Berlekamp–Massey algorithm (BMA) and is capable of generating pre-computed deterministic test patterns which detect the hard-to-detect faults of the circuit. Moreover, the LFSR generates residual patterns which are sufficient to detect the remaining easy-to-detect faults. In this way, the BMA-designed LFSR is a mixed-mode TPG which achieves total fault coverage with short testing length and low hardware overhead compared with previous schemes according to the experimental results.     

一种新型混合模式BIST的低功耗设计

本文提出了一种基于折叠集的test-Der-clock结构的混合模式BIST设计方案,并且进行了低功耗的整体优化设计.该设计方案在电路结构上利用双模式LFSR将两部分测试生成器有机的进行了结合,针对伪随机测试序列与折叠测试序列两部分采用了不同的措施来优化测试生成器的设计,从而达到降低被测电路功耗的目的.     

Application of Deterministic Logic BIST on Industrial Circuits

We present the application of a deterministic logic BIST scheme based on bit-flipping on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for industrial circuits up to 100 K gates with 10,000 test patterns, at a total area cost for BIST hardware of typically 5–15%. It is demonstrated that a trade-off is possible between test quality, test time, and silicon area. In contrast to BIST schemes based on test point insertion no modifications of the circuit under test are required, complete fault efficiency is guaranteed, and the impact on the design process is minimized.     

On the design of random pattern testable PLA based on weighted random pattern testing

Programmable Logic Arrays (PLAs) provide a cost effective method to realize combinational logic circuits. PLAs are often not suitable for random pattern testing due to high fao-in of gates. In order to reduce the effective fan-in of gates, previous random pattern testable (RPT) PLA designs focused on partitioning inputs and product lines. In this paper we propose a new random pattern testable design of PLAs which is suitable for built-in selftest. The key idea of the proposed design is to apply weighted random patterns to the PLA under test. The proposed design method was applied to 30 example PLAs. The performance of the RPT PLAs was measured in the size of test set, area overhead, and time overhead, and compared with two other designs in test length and fault coverage. The experimental results show that the proposed design achieve short test length and high fault coverage.     

Cost-effective LFSR synthesis for optimal pseudoexhaustive BISTtest sets

The generation of pseudoexhaustive test sets for the built-in self-test (BIST) of combinational circuits is addressed, using as a test pattern generator a simple linear feedback register (LFSR), structure, known as LFSR/SR. It is shown that particular orderings of the LFSR cells can significantly reduce the test set size. In addition, it is shown that an LFSR/SK designed with a particular cell ordering and the allowance of a marginal number of additional cells guarantees pseudoexhaustive test sets of the minimum size 2^w, where w is the maximum input dependency limit of the circuit under test. Extensive experimentation on benchmark circuits and comparisons with the hardware overhead of other methods indicate the advantage of this approach     

LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects

For system-on-chips (SoC) using deep submicron (DSM) technologies, interconnects are becoming critical determinants for performance, reliability and power. Buses and long interconnects being susceptible to crosstalk noise, may lead to functional and timing failures. Existing at-speed interconnect crosstalk test methods propose inserting dedicated interconnect self-test structures in the SoC to generate vectors which have high crosstalk defect coverage. However, these methods may have a prohibitively high area overhead. To reduce this overhead, existing logic BIST structures like LFSRs could be reused to deliver interconnect tests. But, as shown by our experiments, use of LFSR tests achieve poor crosstalk defect coverage. Additionally, it has been shown that the power consumed during testing can potentially become a significant concern.In this paper, we present Logic-Interconnect BIST (LI-BIST), a comprehensive self-test solution for both the logic of the cores and the SoC interconnects. LI-BIST reuses existing logic BIST structures but generates high-quality tests for interconnect crosstalk defects, while minimizing the area overhead and interconnect power consumption. The application of the LI-BIST methodology on example SoCs indicates that LI-BIST is a viable, low-cost, yet comprehensive solution for testing SoCs.     

阵列乘法器通路时延故障的内建自测试

阵列乘法器因高度集成和高速运行,容易受到时延故障的困扰.该文对阵列乘法器的通路时延故障提出了一种用累加器实现的以单跳变序列作为测试序列的内建自测试方案.已有的理论和实践表明采用单跳变测试序列比多跳变序列具有更高的测试鲁棒性.同时,该文的测试方案在测试通路覆盖率和测试向量数之间做到了兼顾.仿真结果表明这种单跳变测试序列具有高测试通路覆盖率.此外,测试生成通过系统已有累加器的复用可节省硬件成本开销.     

A current based self-test methodology for RF front-end circuits

This paper presents a critical step in the realization of a robust, low overhead, current-based Built-In Self-Test (BIST) scheme for RF front-end circuits. The proposed approach involves sampling the high frequency supply current drawn by the circuit under test (CUT) and using it to extract information about various performance metrics of the RF CUT. The technique has inherently high fault coverage and can handle soft faults, hard faults as well as concurrent faults because it shifts the emphasis from detecting individual faults, to quantifying all the significant performance specifications of the CUT. This work also presents the realization of an HF current monitor which is a critical component in the proposed architecture. The current monitor has then been interfaced with three standard RF front-end circuits; a Low noise amplifier, a Single Balanced Mixer and a Voltage controlled oscillator, while minimally impacting their performance. The extracted information has then been used to create a mapping between variations in CUT performance and the sensed current spectrum. The monitor circuit has been fabricated in the IBM 6 metal, RF CMOS process, with a gain of 24 db and bandwidth of 3.9 GHz.     

一种新的低功耗内建自测法 􀀂 􀀂 􀀂 线性反馈移位寄存器结构的更改

本文提出了一种通过改变线性反馈移位寄存器（LFSR）的结构实现低功耗内建自测试方法。在伪随机测试方式下，随着测试的进行，测试矢量的效率大幅降低。通过改变线性反馈移位寄存器的结构滤掉无效的测试矢量从而实现低功耗测试。实践证明，改变线性反馈称位寄存器的结构的方法是有效的并且对故障覆盖率没有影响。     

High-efficiency test pattern generating mechanism

A high-efficiency test pattern generating mechanism blending the weighted-random-pattern generator and the controllable-linear-feedback-shift register is proposed in this paper. This mechanism tests a logic circuit in two phases. In the first phase, the weighted-random-pattern generator generates the test patterns to drop some of the faults from the fault list containing the faults that have not been tested in the initial testing performed by the patterns generated from the automatic-test-pattern generator. In the second phase, the controllable-linear-feedback-shift register generates the test patterns to test the deterministic faults that have not been tested in the first phase. We adopt controllable-linear- feedback-shift register to generate the deterministic patterns instead of modifying the configuration of the weighted-random-pattern generator such that a better fault coverage can be achieved with a lower hardware penalty and a shorter test length.     

一种基于受控LFSR的内建自测试结构及其测试矢量生成

本文提出了一种基于受控线性反馈移位寄存器（LFSR）进行内建自测试的结构及其测试矢量生成方法。使用受控LFSR可以跳过伪随机测试序列中对故障覆盖率没有贡献的测试矢量，众而达到减少测试矢量长度，缩短测试时间的目的。     

低成本BIST映射电路的设计与优化

低成本BIST利用映射电路对自测试线形反馈移位寄存器进行优化,将对故障覆盖率无贡献的测试向量屏蔽掉,有效提高了故障覆盖率,降低了测试功耗。映射电路的设计是低成本BIST设计的关键,为了降低其硬件开销和功耗、提高参数性能,该映射逻辑电路对测试向量的种子进行映射,并通过相容逻辑变量合并、布尔代数化简等方法对映射电路进行优化,有效地降低了测试应用时间、测试功耗和硬件开销。