ADI推出手机用小封装低漂移RF功率检测器

<正>模拟器件公司(ADI)日前推出一款用于蜂窝手机的射频(RF)功率检测器--AD8321。该器件帮助制造商在减小系统尺寸的同时进一步提高产品性能。这款低漂移的功率检测器能够在很宽的动态范围内实现精密、温度稳定的功率控制,从而提高性能。     

美国模拟器件公司射频功率检测器

美国模拟器件公司(Analog Devices)推出一款用于蜂窝手机的射频(RF)功率检测器——AD8312，它可使制造商在减小系统尺寸的同时进一步提高性能。这款低漂移AD8312可在很宽动态范围内实现精管，温度稳定的功能控制，     

Hittite宽动态范围的功率检波器

日前，全球知名的射频微波IC厂商Hittite公司面向宽带、3G、Winmax、自动化以及4G应用领域推出了基于SiGe BiCMOS工艺的功率检波器HMC713LP3E。     

光通信用宽动态范围10 Gb/s CMOS跨阻前置放大器

采用UMC 0.13 μm CMOS工艺,设计了一种应用于SDH系统STM-64(10 Gb/s)光接收机前置放大器.该前置放大器采用具有低输入阻抗特点的RGC形式的跨阻放大器实现.同时,引入消直流电路来扩大输入信号的动态范围.后仿真结果表明:双端输出时中频跨阻增益约为57.6 dBΩ,-3 dB带宽为10.7 GHz,平均等效输入噪声电流谱密度为18.76 pA/sqrt(Hz),1.2V单电压源下功耗为21 mW,输入信号动态范围40 dB(10 μA～1 mA).芯片面积为0.462 mm×0.566 mm.     

0.35μm CMOS 2.5Gb/s宽动态范围前置放大器设计

采用Chartered 0.35μm CMOS工艺设计了一种适用于光纤传输系统STM-16(2.5Gb/s)速率级的低功耗、宽动态范围的前置放大器.该前置放大器采用RGC(Regulated Cascode)结构作为输入级,同时引入消直流电路来提高光电流的过载能力.仿真结果表明,前置放大器的跨阻增益为57.0dBΩ,-3dB带宽为2.003GHz;当误码率BER为10~(-12)时,输入灵敏度为-23.0dBm,过载光电流达到800 μ A.3.3V单电源供电时,功耗仅为59.43mW.芯片面积为465 μm × 435 μm.     

一种低噪声、宽动态范围I／F转换器的设计

本文详细介绍了一种低噪声、宽动态范围I／F转换器的设计方法，并给出了设计结果。     

一种含动态缓冲器的宽电源范围低压差线性稳压器

本文提出了一种带有动态缓冲器的宽电源范围低压差线性稳压器（LDO）。该LDO使用0.18μm BCD工艺成功流片并测试,总面积为850μm×1090μm。耐高压的LDMOS用于承受每条路径上的大部分电压,以满足宽电源范围的要求。缓冲器中使用动态电流偏置来降低其输出电阻,从而将传输器件栅极处的极点推至高频,并且不会耗散大的静态电流。本文的LDO在空载情况下消耗16μA静态电流,能在5.5V-40V的宽电源范围内正常工作,典型输出电压为5V,并且在5.5V供电,低压差的情况下能提供70m A负载电流。     

基于0.18μm CMOS工艺2.5Gb/s宽动态范围光接收机前端放大电路设计

基于0.18μm CMOS工艺设计了适用于2.5Gb/s传输速率的宽动态范围光接收机前端放大电路（包括前置放大器和限幅放大器）.前置放大器采用了RGC输入级的跨阻放大器,并且应用了消直流电路和自动增益控制电路扩展输入动态范围.限幅放大器采用了按比例缩小尺寸、并联峰化和带有有源负反馈的Cherry-Hooper放大器等方法扩展带宽.仿真结果表明：前端放大电路的中频增益为116dBΩ,-3dB带宽为2.13GHz,输入信号动态范围为40dB（0.01～1mA）.     

应用于GNSS接收机的宽频带高线性下变频器研究

针对全球导航卫星系统（GNSS）接收机在安全领域的应用要求,提出一种宽频带、高线性和高驱动的新型下变频电路结构.所提出的下变频器由宽频带共栅低噪声跨导放大器、电流型无源混频开关、和增益可调的跨阻驱动放大器组成.该电路采用电容交叉耦合共栅输入跨导增强技术,实现了1.15-1.65 GHz宽频带匹配和全频点GNSS信号的低噪声放大.所提出的新型的桥式跨阻驱动放大器,具有直接驱动50Ω负载阻抗能力,实现了大动态条件下宽增益控制范围和出色的下变频线性性能.流片测试结果表明,提出的下变频器实现了+38 dBm的输出三阶交调截点功率（OIP3）,+17 dBm的输出1 dB压缩点功率（OP1dB）,10-27 dB可调的转换增益.下变频噪声系数（NF）在1.15-1.65 GHz频段的各种增益下都小于12.6dB.该下变频器在低增益模式下实现了高线性、低噪声和强驱动能力,适合应用于复杂环境下的GNSS接收机.     

Low power high gain CMOS LNA based on inverter cell and self-body bias for UWB receivers

A low-power low-noise amplifier (LNA) utilized a resistive inverter configuration feedback amplifier to achieve the broadband input matching purposes. To achieve low power consumption and high gain, the proposed LNA utilizes a current-reused technique and a splitting-load inductive peaking technique of a resistive-feedback inverter for input matching. Two wideband LNAs are implemented by TSMC 0.18 μm CMOS technology. The first LNA operates at 2–6 GHz. The minimum noise figure is 3.6 dB. The amplifier provides a maximum gain (S₂₁) of 18.5 dB while drawing 10.3 mW from a 1.5-V supply. This chip area is 1.028×0.921 mm². The second LNA operates at 3.1–10.6 GHz. By using self-forward body bias, it can reduce supply voltage as well as save bias current. The minimum noise figure is 4.8 dB. The amplifier provides a maximum gain (S₂₁) of 17.8 dB while drawing 9.67 mW from a 1.2-V supply. This chip area is 1.274×0.771 mm².     

采用幅度均衡器的宽带毫米波低噪声放大器

对微带型幅度均衡器进行了理论分析和计算机仿真。微带型均衡器由微带谐振器上加载电阻构成,电阻的引入有效地展宽了频带。通过优化支节的长度、宽带和电阻的阻值,得到满足要求的均衡器。利用这种均衡器,对采用两级毫米波宽带MMIC的放大器进行了增益修正,使增益平坦度得到有效改善,同时对噪声的影响也较小。采用幅度均衡器最终实现的低噪声放大器在频率范围26.5～40 GHz内,增益为26.5～28.5 dB,增益平坦度优于±1.5 dB,噪声小于3.3dB,输入输出端口驻波小于2.0,输出1 dB压缩点功率大于10 dBm。     

射频宽带低噪声放大器的设计与仿真

介绍了一种射频宽带低噪声放大器的设计过程,包括稳定性分析、偏置电路设计和匹配电路设计等内容.设计采用E-PHEMT晶体管(ATF-55143)器件模型和其他元件模型.通过采用ADS技术进行电路和电磁仿真,结果表明设计的放大器完全满足性能指标要求.     

L波段0.9 mW CMOS LNA的分析与设计

给出了一种采用Γ型输入匹配网络的源简并共源低噪声放大器电路结构,分析了在低功耗情况下,高频寄生效应对低噪声放大器(LNA)输入阻抗及噪声特性的影响,并采用此结构设计了一款工作于L渡段的低功耗低噪声放大器.采用CMOS 0.18μm工艺,设计了完整的ESD保护电路,并进行了QFN封装.测试结果表明.在1.57 GHz工作频率下,该低噪声放大器的输入回波损耗小于-30 dB,输出回波损耗小于-14 dB,增益为15.5 dB,噪声系数(NF)为2.4 dB,输入三阶交调点(IIP3)约为-8 dBm.当工作电压为1.5 V时,功耗仅为0.9 mW.     

Design of low power UWB LNA based on common source topology with current-reused technique

This paper presents two low power UWB LNAs with common source topology. The power reduction is achieved by the current-reused technique. The gain and noise enhancement of the proposed circuit is based on an output buffer which is used by a common source amplifier with shunt–shunt feedback. Chip1 is an adopted T-match input network of 50 Ω matching in the required band. Measurements show that the S₁₁ and S₂₂ are less than −10 dB, and the maximum amplifier gain S₂₁ gives 9.7 dB, and the noise figure is 4.2 dB, the IIP3 is −8.5 dBm, and the power consumption is 11 mW from 1.1 V supply voltage. The input matching of chip2 is adopted from a LC high pass filter and source degenerated inductor. The output buffer with the RC-feedback topology can improve the gain, increase the IIP3, restrain the noise, improve the noise figure and decrease the DC power dissipation. Measurements show 13.2 dB of power gain, 3.33 dB of noise figure, and the IIP3 is −3.3 dBm. It consumes 9.3 mW from 1.5 V supply voltage. These two chips are implemented in a 0.18 μm TSMC CMOS process.     

基于ADS仿真的数字对讲机LNA设计

这里首先简单介绍了低噪声放大器（LNA）电路的设计理论,然后介绍了数字对讲机中LNA的设计指标。基于这些指标,使用了HP公司提供的芯片AT-41511,详细阐述了基于ADS仿真的适用于数字对讲机中LNA的主要设计步骤。最后在ADS仿真软件下通过s参数及谐波平衡仿真得到设计出的LNA的各项性能参数,在400-470MHz频率范围内噪声系数小于0．8dB,带内增益大于15dB。仿真结果表明,该设计的LNA可以完全满足所给的性能指标要求。     

New implementation of high linear LNA using derivative superposition method

New implementation of a high linear low-noise amplifier (LNA) using the improved derivative superposition (DS) method is proposed. The input stage is formed by two transistors connected in parallel. One transistor is biased in the strong inversion region as usual and another one is biased in the moderate inversion region instead of the weak inversion region, thus allowing a feasible source degeneration inductance at the sources of the two transistors to achieve a good input impedance matching and low noise figure (NF) while keeping high third-order input intercept point (IIP3) improvement with the DS method. The new implementation has been used in a 0.18-μm CMOS high linear LNA. The measured results show that the LNA achieves +11.92 dBm IIP3 with 9.36 dB gain, 2.25 dB NF and 7.5 mA at 1.8 V power consumption.     

一种电流复用共栅低噪声放大器的低功耗433/915-MHz射频前端的设计

This paper presents a wideband RF front-end with novel current-reuse wide band low noise amplifier(LNA),current-reuse V –I converter,active double balanced mixer and transimpedance amplifier for short range device(SRD) applications.With the proposed current-reuse LNA,the DC consumption of the front-end reduces considerably while maintaining sufficient performance needed by SRD devices.The RF front-end was fabricated in 0.18 μm RFCMOS process and occupies a silicon area of just 0.11 mm2.Operating in 433 MHz band,the measurement results show the RF front-end achieves a conversion gain of 29.7 dB,a double side band noise figure of 9.7 dB,an input referenced third intercept point of –24.9 dBm with only 1.44 mA power consumption from 1.8 V supply.Compared to other reported front-ends,it has an advantage in power consumption.     

Low power high gain gain-controlled LNA and mixer for GNSS receivers Wei Binbin(魏斌斌)1, Jiang Jinguang(江金光)1,2,3*

A low power high gain gain-controlled LNA ＋ mixer for GNSS receivers is reported. The high gain LNA is realized with a current source load. Its gain-controlled ability is achieved using a programmable bias circuit. Taking advantage of the high gain LNA, a high noise figure passive mixer is adopted. With the passive mixer, low power consumption and high voltage gain of the LNA ＋ mixer are achieved. To fully investigate the performance of this circuit, comparisons between a conventional LNA ＋ mixer, a previous low power LNA ＋ mixer, and the proposed LNA ＋ mixer are presented. The circuit is implemented in 0.18 #m mixed-signal CMOS technology. A 3.8 dB noise figure, an overall 45 dB converge gain and a 10 dB controlled gain range of the two stages are measured. The chip occupies 0.24 mm2 and consumes 2 mA current under 1.8 V supply.