4H-SiC MESFET结构与直流特性研究

运用二维器件模拟器ISETCAD对4H-SiCMESFET不同结构的直流特性进行了模拟,重点考虑表面陷阱对直流特性的影响。与凹栅结构相比,埋栅结构的器件降低了表面陷阱对电流的影响,饱和漏电流提高了37%,而且阈值电压的绝对值增大、跨导升高,对提高4H-SiCMES-FET器件的输出功率起到一定的作用。     

High-performance SOI MESFET with modified depletion region using a triple recessed gate for RF applications

A novel SOI MESFET with the modified depletion region using a Triple Recessed Gate (TRG-SOI MESFET) is presented for RF applications. The proposed gate consists of lower and upper gate to control the channel thickness and the depletion layer will change by omitting part of total charge due to locating gate in the channel. The key idea of this shaped gate is to modify the depletion region and the charge distribution of the channel in order to lower the electric field of the device and improving the breakdown voltage. In addition the maximum power density, the maximum oscillation frequency, the cutoff frequency, and the minimum noise figure for the proposed structure are improved due to increasing the drain-source resistance and the transconductance and decreasing the gate resistance. Therefore, the TRG-SOI MESFET can be used for high-power and high frequency applications.     

n沟道4H-SiC MESFET研究

报告了4H-SiCMESFET的研制。通过对SiC关键工艺技术进行研究,设计出初步可行的工艺流程,并且制成单栅宽120μmn沟道4H-SiCMESFET,其主要直流特性为在Vds=30V时,最大漏电流密度Idss为56mA/mm,最大跨导Gm为15mS/mm;漏源击穿电压最高达150V;微波特性测试结果在fo=1GHz、Vds=32V时该器件最大输出功率7.05mW,在fo=1.8GHz、Vds=32V时最大输出功率3.1mW。     

A novel SOI MESFET to spread the potential contours towards the drain

ABSTRACT

This paper presents a new structure of Metal Semiconductor Field Effect Transistor (MESFET) for high power applications. One of the problems that we face in the design of the MESFET devices is that in most cases, the increase of breakdown voltage is accompanied by a decrease in the saturation drain current. Our aim to propose this structure is to improve these two parameters simultaneously. Using the insulator region under the sides of the gate (IR) and the hide field plate (HFP) in the buried oxide (BOX) are the fundamental solution for improving these parameters. We named the proposed structure as spread potential contours towards the drain MESFET (SPC-MESFET). By applying the proposed structure, the drain current and the breakdown voltage improve 20 and 27 percent compared to a conventional structure (C-MESFET), respectively. Therefore, the proposed device has a higher maximum power density than the C-MESFET structure. Also, this idea reduces the gate capacitance and thus the frequency characteristics such as cut off frequency (f_T), maximum oscillation frequency (f_max), and Maximum Available Gain (MAG) improve in comparison with the C-MESFET structure.     

基于实验与物理分析的4H-SiC射频功率MESFET大信号非线性精确电容模型

采用电荷控制理论和载流子速度饱和理论的物理分析方法,并结合Statz、Angelov等经验模型的描述方法,提出了常温下针对4H-SiC射频功率MESFET的大信号非线性电容模型.此模型在低漏源偏压区对栅源电容Cgs强非线性的描述优于Statz、Angelov等经验模型,计算量也远低于基于器件物理特性的数值模型,因而适合于大信号的电路设计与优化.     

基于改进陷阱模型的新型p型隔离层结合场板结构的4H-SiC MESFET的特性研究与优化

本文提出了一种致力于抑制表面陷阱影响的新型结构。基于能准确表征4H-SiC材料特性的物理模型和经过实验证明能较好表征表面陷阱作用机理的模型,对器件的特性进行了研究。通过与实际器件制作中主流采用的埋栅-场板结构的4H-SiC MESFET以及实验测试的器件特性的对比,本文提出的结构在整体上对器件的特性有所提高 。新结构引入的 p型隔离层能有效地抑制表面陷阱的影响并且能减小器件在大电压微波应用条件下的栅漏电容;P型隔离层结合场板结构改善了栅极边缘的电场分布,同时能减小单一使用场板结构时场板对沟道引入的附加栅漏电容; 作为微波晶体管,由于更好的抑制了表面陷阱,基于本文提出的结构的4H-SiC MESFET比埋栅-场板结构的器件具有更高的栅延迟抑制比;在实现大功率应用方面,新型结构同样能提供更高的耐压。新结构的4H-SiC MESFET的最大饱和漏电流密度为460mA/mm,在漏电压20V的栅延迟抑制比接近90%。交流特性的分析结果表明,本文提出的结构比埋栅-场板结构的器件的特征频率和最高振荡频率分别高出5%和17.8%。此外,新结构的器件能承受较高的击穿电压,进而保证了器件的大功率密度。针对本文提出的结构进行了优化,以使器件能发挥最好的微波特性并对器件的设计提供一定参考。     

Characteristics and optimization of 4H-SiC MESFET with a novel p-type spacer layer incorporated with a field-plate structure based on improved trap models

A novel structure of 4H-SiC MESFETs is proposed that focuses on surface trap suppression.Characteristics of the device have been investigated based on physical models for material properties and improved trap models.By comparing with the performance of the well-utilized buried-gate incorporated with a field-plate （BG-FP） structure,it is shown that the proposed structure improves device properties in comprehensive aspects. A p-type spacer layer introduced in the channel layer suppresses the surface trap effect and reduces the gate-drain capacitance(C_gd) under a large drain voltage.A p-type spacer layer incorporated with a field-plate improves the electric field distribution on the gate edge while the spacer layer induces less C_gd than a conventional FP.For microwave applications,4H-SiC MESFET for the proposed structure has a larger gate-lag ratio in the saturation region due to better surface trap isolation from the conductive channel.For high power applications,the proposed structure is able to endure higher operating voltage as well.The maximum saturation current density of 460 mA/mm is yielded.Also,the gate-lag ratio under a drain voltage of 20 V is close to 90%.In addition,5%and 17.8%improvements in f_T and f_max are obtained compared with a BG-FP MESFET in AC simulation,respectively.Parameters and dimensions of the proposed structure are optimized to make the best of the device for microwave applications and to provide a reference for device design.     

Recessed p-buffer layer SiC MESFET: A novel device for improving DC and RF characteristics

This is the first report of novel structures designated as recessed p-buffer (RPB) silicon carbide (SiC) metal semiconductor field effect transistors (MESFETs). Important parameters such as gate–source capacitance, short channel effect, DC trans-conductance, cut-off frequency, DC output conductance, drain current and breakdown voltage of the two structures, the source side-recessed p-buffer (SS-RPB) and drain side-recessed p-buffer (DS-RPB), are simulated and compared with the conventional recessed gate SiC MESFET. Our simulation results describe that reducing the channel thickness under the gate at the source side of the SS-RPB structure, improves the gate–source capacitance, DC trans-conductance, and cut-off frequency compared with DS-RPB and conventional structures. Short channel effects for the SS-RPB structure are improved compared with that of the DS-RPB structure. Also, the SS-RPB structure has smaller DC output conductance in comparison with the conventional and DS-RPB structures. However, saturated drain current and breakdown voltage in the DS-RPB structure is larger than those in the conventional and SS-RPB structures.     

A 4H-SiC semi-super-junction shielded trench MOSFET: p-pillar is grounded to optimize the electric field characteristics

A 4H-SiC trench gate metal–oxide–semiconductor field-effect transistor (UMOSFET) with semi-super-junction shielded structure (SS-UMOS) is proposed and compared with conventional trench MOSFET (CT-UMOS) in this work. The advantage of the proposed structure is given by comprehensive study of the mechanism of the local semi-super-junction structure at the bottom of the trench MOSFET. In particular, the influence of the bias condition of the p-pillar at the bottom of the trench on the static and dynamic performances of the device is compared and revealed. The on-resistance of SS-UMOS with grounded (G) and ungrounded (NG) p-pillar is reduced by 52% (G) and 71% (NG) compared to CT-UMOS, respectively. Additionally, gate oxide in the GSS-UMOS is fully protected by the p-shield layer as well as semi-super-junction structure under the trench and p-base regions. Thus, a reduced electric-field of 2 MV/cm can be achieved at the corner of the p-shield layer. However, the quasi-intrinsic protective layer cannot be formed in NGSS-UMOS due to the charge storage effect in the floating p-pillar, resulting in a large electric field of 2.7 MV/cm at the gate oxide layer. Moreover, the total switching loss of GSS-UMOS is 1.95 mJ/cm² and is reduced by 18% compared with CT-UMOS. On the contrary, the NGSS-UMOS has the slowest overall switching speed due to the weakened shielding effect of the p-pillar and the largest gate-to-drain capacitance among the three. The proposed GSS-UMOS plays an important role in high-voltage and high-frequency applications, and will provide a valuable idea for device design and circuit applications.     

A review of the etched terminal structure of a 4H-SiC PiN diode

The comparison of domestic and foreign studies has been utilized to extensively employ junction termination extension (JTE) structures for power devices. However, achieving a gradual doping concentration change in the lateral direction is difficult for SiC devices since the diffusion constants of the implanted aluminum ions in SiC are much less than silicon. Many previously reported studies adopted many new structures to solve this problem. Additionally, the JTE structure is strongly sensitive to the ion implantation dose. Thus, GA-JTE, double-zone etched JTE structures, and SM-JTE with modulation spacing were reported to overcome the above shortcomings of the JTE structure and effectively increase the breakdown voltage. They provided a theoretical basis for fabricating terminal structures of 4H-SiC PiN diodes. This paper summarized the effects of different terminal structures on the electrical properties of SiC devices at home and abroad. Presently, the continuous development and breakthrough of terminal technology have significantly improved the breakdown voltage and terminal efficiency of 4H-SiC PiN power diodes.     

一种降低VDMOS导通电阻的新结构研究

本文提出了一种降低VDMOS导通电阻的新结构,从理论上分析了该结构在保证VDMOS器件击穿电压保持不变的前提下,可以降低VDMOS的比导通电阻约22%,同时该新结构仅需要在原VDMOS器件版图的基础上增加一个埋层,工艺可加工性较强。把该结构用于一款200V耐压的N沟道VDMOS器件的仿真分析,器件元胞的比导通电阻降低了23%,采用三次外延四次埋层的制作方式,器件的比导通电阻可以降低33%,该新结构在条栅VDMOS研制方面具有广阔的应用前景。     

A novel structure in reducing the on-resistance of a VDMOS

A novel structure of a VDMOS in reducing on-resistance is proposed.With this structure,the specific on-resistance value of the VDMOS is reduced by 22%of that of the traditional VDMOS structure as the breakdown voltage maintained the same value in theory,and there is only one additional mask in processing the new structure VDMOS,which is easily fabricated.With the TCAD tool,one 200 V N-channel VDMOS with the new structure is analyzed,and simulated results show that a specific on-resistance value will reduce by 23%,and the value by 33% will be realized when the device is fabricated in three epitaxies and four buried layers.The novel structure can be widely used in the strip-gate VDMOS area.     

基于漏区边界曲率分析的射频RESURF LDMOS耐压与导通电阻优化

分析了漏区边界曲率半径与射频RESURF LDMOS击穿电压的关系,指出漏区边界的弯曲对RESURF技术的效果具有强化作用.理论分析与模拟结果表明,满足RESURF条件时,提高漂移区掺杂浓度或掺杂深度的同时相应减小漏区边界的曲率半径,可以在维持击穿电压不变的前提下,明显降低导通电阻.     

A charge allocating model for the breakdown voltage calculation and optimization of the lateral RESURF devices

A new quite simple analytical model based on the charge allocating approach has been proposed to describe the breakdown property of the RESURF (reduced surface field) structure. It agrees well with the results of numerical simulation on predicting the breakdown voltage. Compared with the latest published analytical model, this model has a better accuracy according to the numerical simulation with simpler form. The optimal doping concentration (per unit area) of the epi-layer of the RESURF structures with different structure parameters has been calculated based on this model and the results show no significant discrepancy to the data gained by others. Additionally the physical mechanism of how the surface field is reduced is clearly illustrated by this model.     

A new static induction thyristor with high forward blocking voltage and excellent switching performances

A new static induction thyristor (SITH) with a strip anode region and p~- buffer layer structure (SAP-B) has been successfully designed and fabricated. This structure is composed of a p~- buffer layer and lightly doped n~-regions embedded in the p~+-emitter. Compared with the conventional structure of a buried-gate with a diffused source region (DSR buried-gate), besides the simple fabrication process, the forward blocking voltage of this SITH has been increased to 1600 V from the previous value of 1000 V, the blocking gain increased from 40 to 70, and the turn-off time decreased from 0.8 to 0.4μs.     

一种具有高正向阻断电压及优良开关特性的新型静电感应晶闸管

设计并构造了一种具有条状阳极P-缓冲层结构（SAP-B）的新型静电感应晶闸管。该结构以具有p- 缓冲层和嵌入p+发射区（条状阳极区）的弱掺杂n-发射区（泄漏阳极区）为特点。与传统扩散源区埋栅结构相比,SAP-B结构可进一步简化工艺,并将扩散源区埋栅结构静电感应晶闸管的正向阻断电压从1000V提高至1600V,阻断增益从40提高至70,同时将关断时间从0.8μs降低至0.4μs。     

A novel high-voltage device structure with an N~+ ring in substrate and the breakdown voltage model

A novel high-voltage device structure with a floating heavily doped N~+ ring embedded in the substrate is reported,which is called FR LDMOS.When the N~+ ring is introduced in the device substrate,the electric field peak of the main junction is reduced due to the transfer of the voltage from the main junction to the N~+ ring junction, and the vertical breakdown characteristic is improved significantly.Based on the Poisson equation of cylindrical coordinates,a breakdown voltage model is developed.The numerical results indicate that the breakdown voltage of the proposed device is increased by 56%in comparison to conventional LDMOS.     

衬底浮空N 环高压器件新结构与击穿电压模型

提出带有衬底重掺杂N 环的高压器件新结构,称为FR LDMOS。在衬底中引入高掺杂N 环,漏极偏压由环结和漂移区主结分担,降低了主结电场,纵向击穿特性获得显著改善。基于柱坐标Poisson方程,建立击穿电压模型。结果表明：FR LDMOS较常规器件击穿电压提高56%。     

栅槽横向宽度对InAlAs/InGaAs HEMTsDC及RF特性的影响

我们制造出了栅长为88 nm的InP基InAlAs/InGaAs 高电子迁移率器件(HEMTs),该器件的频率特性为ft = 100 GHz, fmax = 185 GHz。本文对横向栅槽宽度分别为300 nm, 412 nm, 1070 nm的器件进行了实验。借助能带图的方式,定性分析了横向栅宽的增加会因为表面态和碰撞电离的作用,使得器件直流特性表现出kink效应,并得到减小横向栅槽宽度能减弱kink效应的结论,文中还讨论了横向栅槽宽度通过改变器件寄生电容及其源漏电阻,从而对频率特性产生影响。这些分析对制造出更高性能的HEMT器件有比较重要的意义。